1/* $NetBSD: mipsNN.h,v 1.14 2023/05/06 21:53:26 andvar Exp $ */ 2 3/* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. The "Broadcom Corporation" name may not be 19 * used to endorse or promote products derived from this software 20 * without the prior written permission of Broadcom Corporation. 21 * 22 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 25 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 26 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 27 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 32 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * Values related to the MIPS32/MIPS64 Privileged Resource Architecture. 37 */ 38 39#define _MIPSNN_SHIFT(reg) __MIPSNN_SHIFT(reg) 40#define __MIPSNN_SHIFT(reg) MIPSNN_ ## reg ## _SHIFT 41#define _MIPSNN_MASK(reg) __MIPSNN_MASK(reg) 42#define __MIPSNN_MASK(reg) MIPSNN_ ## reg ## _MASK 43 44#define MIPSNN_GET(reg, x) \ 45 ((unsigned)((x) & _MIPSNN_MASK(reg)) >> _MIPSNN_SHIFT(reg)) 46#define MIPSNN_PUT(reg, val) \ 47 (((x) << _MIPSNN_SHIFT(reg)) & _MIPSNN_MASK(reg)) 48 49/* 50 * Values in Configuration Register (CP0 Register 16, Select 0) 51 */ 52 53/* "M" (R): Configuration Register 1 present if set. Defined as always set. */ 54#define MIPSNN_CFG_M 0x80000000 55 56/* Reserved for CPU implementations. */ 57// reserved 0x7fff0000 58 59/* "BE" (R): Big endian if set, little endian if clear. */ 60#define MIPSNN_CFG_BE 0x00008000 61 62/* "AT" (R): architecture type implemented by processor */ 63#define MIPSNN_CFG_AT_MASK 0x00006000 64#define MIPSNN_CFG_AT_SHIFT 13 65 66#define MIPSNN_CFG_AT_MIPS32 0 /* MIPS32 */ 67#define MIPSNN_CFG_AT_MIPS64S 1 /* MIPS64S */ 68#define MIPSNN_CFG_AT_MIPS64 2 /* MIPS64 */ 69// reserved 3 70 71/* "AR" (R): Architecture revision level implemented by proc. */ 72#define MIPSNN_CFG_AR_MASK 0x00001c00 73#define MIPSNN_CFG_AR_SHIFT 10 74 75#define MIPSNN_CFG_AR_REV1 0 /* Revision 1 */ 76#define MIPSNN_CFG_AR_REV2 1 /* Revision 2 */ 77// reserved other values 78 79/* "MT" (R): MMU type implemented by processor */ 80#define MIPSNN_CFG_MT_MASK 0x00000380 81#define MIPSNN_CFG_MT_SHIFT 7 82 83#define MIPSNN_CFG_MT_NONE 0 /* No MMU */ 84#define MIPSNN_CFG_MT_TLB 1 /* Std TLB */ 85#define MIPSNN_CFG_MT_BAT 2 /* Std BAT */ 86#define MIPSNN_CFG_MT_FIXED 3 /* Std Fixed mapping */ 87// reserved other values 88 89/* Reserved. Write as 0, reads as 0. */ 90// reserved 0x00000070 91 92/* "M" (R): Virtual instruction cache if set. */ 93#define MIPSNN_CFG_VI 0x00000008 94 95/* "K0" (RW): Kseg0 coherency algorithm. (values are TLB_ATTRs) */ 96#define MIPSNN_CFG_K0_MASK 0x00000007 97#define MIPSNN_CFG_K0_SHIFT 0 98 99 100/* 101 * Values in Configuration Register 1 (CP0 Register 16, Select 1) 102 */ 103 104/* M (R): Configuration Register 2 present. */ 105#define MIPSNN_CFG1_M 0x80000000 106 107/* MS (R): Number of TLB entries - 1. */ 108#define MIPSNN_CFG1_MS_MASK 0x7e000000 109#define MIPSNN_CFG1_MS_SHIFT 25 110 111#define MIPSNN_CFG1_MS(x) (MIPSNN_GET(CFG1_MS, (x)) + 1) 112 113/* "IS" (R): (Primary) I-cache sets per way. */ 114#define MIPSNN_CFG1_IS_MASK 0x01c00000 115#define MIPSNN_CFG1_IS_SHIFT 22 116 117#define MIPSNN_CFG1_IS_RSVD 7 /* rsvd value, otherwise: */ 118#define MIPSNN_CFG1_IS(x) (64 << MIPSNN_GET(CFG1_IS, (x))) 119 120/* "IL" (R): (Primary) I-cache line size. */ 121#define MIPSNN_CFG1_IL_MASK 0x00380000 122#define MIPSNN_CFG1_IL_SHIFT 19 123 124#define MIPSNN_CFG1_IL_NONE 0 /* No I-cache, */ 125#define MIPSNN_CFG1_IL_RSVD 7 /* rsvd value, otherwise: */ 126#define MIPSNN_CFG1_IL(x) (2 << MIPSNN_GET(CFG1_IL, (x))) 127 128/* "IA" (R): (Primary) I-cache associativity (ways - 1). */ 129#define MIPSNN_CFG1_IA_MASK 0x00070000 130#define MIPSNN_CFG1_IA_SHIFT 16 131 132#define MIPSNN_CFG1_IA(x) MIPSNN_GET(CFG1_IA, (x)) 133 134/* "DS" (R): (Primary) D-cache sets per way. */ 135#define MIPSNN_CFG1_DS_MASK 0x0000e000 136#define MIPSNN_CFG1_DS_SHIFT 13 137 138#define MIPSNN_CFG1_DS_RSVD 7 /* rsvd value, otherwise: */ 139#define MIPSNN_CFG1_DS(x) (64 << MIPSNN_GET(CFG1_DS, (x))) 140 141/* "DL" (R): (Primary) D-cache line size. */ 142#define MIPSNN_CFG1_DL_MASK 0x00001c00 143#define MIPSNN_CFG1_DL_SHIFT 10 144 145#define MIPSNN_CFG1_DL_NONE 0 /* No D-cache, */ 146#define MIPSNN_CFG1_DL_RSVD 7 /* rsvd value, otherwise: */ 147#define MIPSNN_CFG1_DL(x) (2 << MIPSNN_GET(CFG1_DL, (x))) 148 149/* "DA" (R): (Primary) D-cache associativity (ways - 1). */ 150#define MIPSNN_CFG1_DA_MASK 0x00000380 151#define MIPSNN_CFG1_DA_SHIFT 7 152 153#define MIPSNN_CFG1_DA(x) MIPSNN_GET(CFG1_DA, (x)) 154 155/* "C2" (R): Coprocessor 2 implemented if set. */ 156#define MIPSNN_CFG1_C2 0x00000040 157 158/* "MD" (R): MDMX ASE implemented if set. */ 159#define MIPSNN_CFG1_MD 0x00000020 160 161/* "PC" (R): Performance Counters implemented if set. */ 162#define MIPSNN_CFG1_PC 0x00000010 163 164/* "WR" (R): Watch registers implemented if set. */ 165#define MIPSNN_CFG1_WR 0x00000008 166 167/* "CA" (R): Code compressiong (MIPS16) implemented if set. */ 168#define MIPSNN_CFG1_CA 0x00000004 169 170/* "EP" (R): EJTAG implemented if set. */ 171#define MIPSNN_CFG1_EP 0x00000002 172 173/* "FP" (R): FPU implemented if set. */ 174#define MIPSNN_CFG1_FP 0x00000001 175 176/* 177 * Values in Configuration Register 2 (CP0 Register 16, Select 2) 178 */ 179 180/* "M" (R): Configuration Register 3 present. */ 181#define MIPSNN_CFG2_M 0x80000000 182 183/* "TU" (RW): Implementation specific tertiary cache status and control. */ 184#define MIPSNN_CFG2_TU_MASK 0x70000000 185#define MIPSNN_CFG2_TU_SHIFT 28 186 187/* "TS" (R): Tertiary cache sets per way. */ 188#define MIPSNN_CFG2_TS_MASK 0x07000000 189#define MIPSNN_CFG2_TS_SHIFT 24 190 191#define MIPSNN_CFG2_TS(x) (64 << MIPSNN_GET(CFG2_TS, (x))) 192 193/* "TL" (R): Tertiary cache line size. */ 194#define MIPSNN_CFG2_TL_MASK 0x00700000 195#define MIPSNN_CFG2_TL_SHIFT 20 196 197#define MIPSNN_CFG2_TL_NONE 0 /* No Tertiary cache */ 198#define MIPSNN_CFG2_TL(x) (2 << MIPSNN_GET(CFG2_TL, (x))) 199 200/* "TA" (R): Tertiary cache associativity (ways - 1). */ 201#define MIPSNN_CFG2_TA_MASK 0x00070000 202#define MIPSNN_CFG2_TA_SHIFT 16 203 204#define MIPSNN_CFG2_TA(x) MIPSNN_GET(CFG2_TA, (x)) 205 206/* "SU" (RW): Implementation specific secondary cache status and control. */ 207#define MIPSNN_CFG2_SU_MASK 0x0000f000 208#define MIPSNN_CFG2_SU_SHIFT 12 209 210/* "SS" (R): Secondary cache sets per way. */ 211#define MIPSNN_CFG2_SS_MASK 0x00000700 212#define MIPSNN_CFG2_SS_SHIFT 8 213 214#define MIPSNN_CFG2_SS(x) (64 << MIPSNN_GET(CFG2_SS, (x))) 215 216/* "SL" (R): Secdonary cache line size. */ 217#define MIPSNN_CFG2_SL_MASK 0x00000070 218#define MIPSNN_CFG2_SL_SHIFT 4 219 220#define MIPSNN_CFG2_SL_NONE 0 /* No Secondary cache */ 221#define MIPSNN_CFG2_SL(x) (2 << MIPSNN_GET(CFG2_SL, (x))) 222 223/* "SA" (R): Secondary cache associativity (ways - 1). */ 224#define MIPSNN_CFG2_SA_MASK 0x00000007 225#define MIPSNN_CFG2_SA_SHIFT 0 226 227#define MIPSNN_CFG2_SA(x) MIPSNN_GET(CFG2_SA, (x)) 228 229/* 230 * Values in Configuration Register 3 (CP0 Register 16, Select 3) 231 */ 232 233/* "M" (R): Configuration Register 4 present. */ 234#define MIPSNN_CFG3_M 0x80000000 235 236/* "BPG" (R): Big Pages feature is implemented (PageMask is 64-bits wide). */ 237#define MIPSNN_CFG3_BPG 0x40000000 238 239/* "CMGCR" (R): Coherency Manager memory-mapped Global Configuration Register Space is implemented. */ 240#define MIPSNN_CFG3_CMGCR 0x20000000 241 242/* "IPLW" (R): Width of Status[IPL] and Cause[RIPL] fields. */ 243#define MIPSNN_CFG3_IPLW_MASK 0x00600000 244#define MIPSNN_CFG3_IPLW_SHIFT 21 245 246#define MIPSNN_CFG3_IPLW_6BITS 0 /* IPL and RIPL fields are 6-bits in width. */ 247#define MIPSNN_CFG3_IPLW_8BITS 1 /* IPL and RIPL fields are 8-bits in width. */ 248// reserved other values 249 250#define MIPSNN_CFG3_MMAR_MASK 0x001c0000 251#define MIPSNN_CFG3_MMAR_SHIFT 18 252 253#define MIPSNN_CFG3_MMAR_REV1 0 /* Revision 1 */ 254// reserved other values 255 256/* "MCU" (R): MCU ASE extension present. */ 257#define MIPSNN_CFG3_MCU 0x00020000 258 259/* "ISAOnExc" (R/RW): ISA used on exception. */ 260#define MIPSNN_CFG3_ISAOnExc 0x00010000 /* microMIPS used on entrance to exception vector */ 261 262/* "ISA" (R): Instruction Set Availability. */ 263#define MIPSNN_CFG3_ISA_MASK 0x0000c000 264#define MIPSNN_CFG3_ISA_SHIFT 14 265 266#define MIPSNN_CFG3_ISA_MIPS64 0 /* only MIPS64 */ 267#define MIPSNN_CFG3_ISA_microMIPS64 1 /* only microMIPS64 */ 268#define MIPSNN_CFG3_ISA_MIPS64_OOR 2 /* both, MIPS64 out of reset */ 269#define MIPSNN_CFG3_ISA_microMIPS64_OOR 3 /* both, microMIPS64 OOR */ 270 271/* "ULRI" (R): UserLocal register is implemented. */ 272#define MIPSNN_CFG3_ULRI 0x00002000 273 274/* "DSP2P" (R): DSP v2 ASE extension present. */ 275#define MIPSNN_CFG3_DSP2P 0x00000800 276 277/* "DSPP" (R): DSP ASE extension present. */ 278#define MIPSNN_CFG3_DSPP 0x00000400 279 280/* "LPA" (R): Large physical addresses implemented. (MIPS64 rev 2 only). */ 281#define MIPSNN_CFG3_LPA 0x00000080 282 283/* "VEIC" (R): External interrupt controller present. (rev 2 only). */ 284#define MIPSNN_CFG3_VEIC 0x00000040 285 286/* "VINT" (R): Vectored interrupts implemented. (rev 2 only). */ 287#define MIPSNN_CFG3_VINT 0x00000020 288 289/* "SP" (R): Small (1K) page support implemented. (rev 2 only). */ 290#define MIPSNN_CFG3_SP 0x00000010 291 292/* "MT" (R): MT ASE extension implemented. */ 293#define MIPSNN_CFG3_MT 0x00000004 294 295/* "SM" (R): SmartMIPS ASE extension implemented. */ 296#define MIPSNN_CFG3_SM 0x00000002 297 298/* "TL" (R): Trace Logic implemented. */ 299#define MIPSNN_CFG3_TL 0x00000001 300 301/* 302 * Values in Configuration Register 4 (CP0 Register 16, Select 4) 303 */ 304 305/* "M" (R): Configuration Register 5 present. */ 306#define MIPSNN_CFG4_M __BIT(31) 307 308/* "IE" (R): TLB invalidate instruction support/configuration. */ 309#define MIPSNN_CFG4_IE __BITS(30,29) 310 311/* "AE" (R): Extend EntryHi[ASID] to 10 bits. */ 312#define MIPSNN_CFG4_AE __BIT(28) 313 314/* "VTLBSizeExt" (R): TLB invalidate instruction support/configuration. */ 315#define MIPSNN_CFG4_VTLB_SE __BITS(27,24) 316 317/* "KScrExist" (R): Number of kernel mode scratch registers available. */ 318#define MIPSNN_CFG4_KSCR_EXIST __BITS(23,16) 319 320/* "MMUExtDef" (R): MMU extension definition. */ 321#define MIPSNN_CFG4_MMU_EXT_DEF __BITS(15,14) 322#define MIPSNN_CFG4_MMU_EXT_DEF_MMU 1 323#define MIPSNN_CFG4_MMU_EXT_DEF_FLTB 2 324#define MIPSNN_CFG4_MMU_EXT_DEF_VTLB 3 325 326/* "MMUSizeExt" (R): Extension of Config1[MMUSize-1] field. */ 327#define MIPSNN_CFG4_MMU_SIZE_EXT __BITS(7,0) 328 329/* "FTLBPageSize" (R/RW): Indicates the Page Size of the FTLB Array Entries. */ 330#define MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE __BITS(10,8) 331#define MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_1K 0 332#define MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_4K 1 333#define MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_16K 2 334#define MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_64K 3 335#define MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_256K 4 336#define MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_1G 5 337#define MIPSNN_CFG4_FTLB_FTLB_PAGE_SIZE_4G 6 338/* "FTLBWays" (R): Indicates the Set Associativity of the FTLB Array. */ 339#define MIPSNN_CFG4_FTLB_FTLB_WAYS __BITS(7,4) 340#define MIPSNN_CFG4_FTLB_FTLB_WAYS_2 0 341#define MIPSNN_CFG4_FTLB_FTLB_WAYS_3 1 342#define MIPSNN_CFG4_FTLB_FTLB_WAYS_4 2 343#define MIPSNN_CFG4_FTLB_FTLB_WAYS_5 3 344#define MIPSNN_CFG4_FTLB_FTLB_WAYS_6 4 345#define MIPSNN_CFG4_FTLB_FTLB_WAYS_7 5 346#define MIPSNN_CFG4_FTLB_FTLB_WAYS_8 6 347/* "FTLBSets" (R): Indicates the number of Set per Way within the FTLB Array. */ 348#define MIPSNN_CFG4_FTLB_FTLB_SETS __BITS(3,0) 349#define MIPSNN_CFG4_FTLB_FTLB_SETS_1 0 350#define MIPSNN_CFG4_FTLB_FTLB_SETS_2 1 351#define MIPSNN_CFG4_FTLB_FTLB_SETS_4 2 352#define MIPSNN_CFG4_FTLB_FTLB_SETS_8 3 353#define MIPSNN_CFG4_FTLB_FTLB_SETS_16 4 354#define MIPSNN_CFG4_FTLB_FTLB_SETS_32 5 355#define MIPSNN_CFG4_FTLB_FTLB_SETS_64 6 356#define MIPSNN_CFG4_FTLB_FTLB_SETS_128 7 357#define MIPSNN_CFG4_FTLB_FTLB_SETS_256 8 358#define MIPSNN_CFG4_FTLB_FTLB_SETS_512 9 359#define MIPSNN_CFG4_FTLB_FTLB_SETS_1024 10 360#define MIPSNN_CFG4_FTLB_FTLB_SETS_2048 11 361#define MIPSNN_CFG4_FTLB_FTLB_SETS_4096 12 362#define MIPSNN_CFG4_FTLB_FTLB_SETS_8192 13 363#define MIPSNN_CFG4_FTLB_FTLB_SETS_16384 14 364#define MIPSNN_CFG4_FTLB_FTLB_SETS_32768 15 365 366/* "MMUSizeExt" (R): Extension of Config1[MMUSize-1] field. */ 367#define MIPSNN_CFG4_FVTLB_VTLB_SIZE_EXT __BITS(27,24) 368/* "FTLBPageSize" (R/RW): Indicates the Page Size of the FTLB Array Entries. */ 369#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE __BITS(12,8) 370#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_1K 0 371#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_4K 1 372#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_16K 2 373#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_64K 3 374#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_256K 4 375#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_1M 5 376#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_4M 6 377#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_16M 7 378#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_64M 8 379#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_256M 9 380#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_1G 10 381#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_4G 11 382#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_16G 12 383#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_64G 13 384#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_256G 14 385#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_1T 15 386#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_4T 16 387#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_16T 17 388#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_64T 18 389#define MIPSNN_CFG4_FVTLB_FTLB_PAGE_SIZE_256T 19 390/* "FTLBWays" (R): Indicates the Set Associativity of the FTLB Array. */ 391#define MIPSNN_CFG4_FVTLB_FTLB_WAYS __BITS(7,4) 392#define MIPSNN_CFG4_FVTLB_FTLB_WAYS_2 0 393#define MIPSNN_CFG4_FVTLB_FTLB_WAYS_3 1 394#define MIPSNN_CFG4_FVTLB_FTLB_WAYS_4 2 395#define MIPSNN_CFG4_FVTLB_FTLB_WAYS_5 3 396#define MIPSNN_CFG4_FVTLB_FTLB_WAYS_6 4 397#define MIPSNN_CFG4_FVTLB_FTLB_WAYS_7 5 398#define MIPSNN_CFG4_FVTLB_FTLB_WAYS_8 6 399/* "FTLBSets" (R): Indicates the number of Set per Way within the FTLB Array. */ 400#define MIPSNN_CFG4_FVTLB_FTLB_SETS __BITS(3,0) 401#define MIPSNN_CFG4_FVTLB_FTLB_SETS_1 0 402#define MIPSNN_CFG4_FVTLB_FTLB_SETS_2 1 403#define MIPSNN_CFG4_FVTLB_FTLB_SETS_4 2 404#define MIPSNN_CFG4_FVTLB_FTLB_SETS_8 3 405#define MIPSNN_CFG4_FVTLB_FTLB_SETS_16 4 406#define MIPSNN_CFG4_FVTLB_FTLB_SETS_32 5 407#define MIPSNN_CFG4_FVTLB_FTLB_SETS_64 6 408#define MIPSNN_CFG4_FVTLB_FTLB_SETS_128 7 409#define MIPSNN_CFG4_FVTLB_FTLB_SETS_256 8 410#define MIPSNN_CFG4_FVTLB_FTLB_SETS_512 9 411#define MIPSNN_CFG4_FVTLB_FTLB_SETS_1024 10 412#define MIPSNN_CFG4_FVTLB_FTLB_SETS_2048 11 413#define MIPSNN_CFG4_FVTLB_FTLB_SETS_4096 12 414#define MIPSNN_CFG4_FVTLB_FTLB_SETS_8192 13 415#define MIPSNN_CFG4_FVTLB_FTLB_SETS_16384 14 416#define MIPSNN_CFG4_FVTLB_FTLB_SETS_32768 15 417 418 419/* 420 * Values in Configuration Register 5 (CP0 Register 16, Select 5) 421 */ 422 423/* "M" (R): Reserved for undefined configuration present. */ 424#define MIPSNN_CFG5_M __BIT(31) 425 426/* "K" (RW): Enable/disable Config K0/Ku/K23 if segmentation is implemented. */ 427#define MIPSNN_CFG5_K __BIT(30) 428 429/* "CV" (RW): Cache Error Exception Vector control disable. */ 430#define MIPSNN_CFG5_CV __BIT(29) 431 432/* "EVA" (R): Enhanced Virtual Addressing instructions implemented. */ 433#define MIPSNN_CFG5_EVA __BIT(28) 434 435/* "MSAEn" (RW): MIPS SIMD Architecture (MSA) enable. */ 436#define MIPSNN_CFG5_MSAEn __BIT(27) 437 438/* "XNP" (R): Extended LL/SC instructions non present. */ 439#define MIPSNN_CFG5_XNP __BIT(13) 440 441/* "DEC" (R): Dual Endian Capability. */ 442#define MIPSNN_CFG5_DEC __BIT(11) 443 444/* "L2C" (R): Indicates presense of COP0 Config2. */ 445#define MIPSNN_CFG5_L2C __BIT(10) 446 447/* "UFE" (RW): Enable for user mode access to Config5[FRE]. */ 448#define MIPSNN_CFG5_UFE __BIT(9) 449 450/* "FRE" (RW): Enable for user mode to emulate Status[FR]=0 handling. */ 451#define MIPSNN_CFG5_FRE __BIT(8) 452 453/* "VP" (R): Virtual Processor - multi-threading features supported. */ 454#define MIPSNN_CFG5_VP __BIT(7) 455 456/* "SBRI" (RW): SDBBP instruction Reserved Instruction control. */ 457#define MIPSNN_CFG5_SBRI __BIT(6) 458 459/* "MVH" (R): Move To/From High COP0 (MTHCO/MFHCO) instructions implemented. */ 460#define MIPSNN_CFG5_MVH __BIT(5) 461 462/* "LLB" (R): Load-Linked Bit (LLB) is present in COP0 LLAddr. */ 463#define MIPSNN_CFG5_LLB __BIT(4) 464 465/* "MRP" (R): COP0 Memory Accessibility Attributes Registers are present. */ 466#define MIPSNN_CFG5_MRP __BIT(3) 467 468/* "UFR" (R): Allows user-mode access to Status[FR] using CTC1/CFC1. */ 469#define MIPSNN_CFG5_UFR __BIT(2) 470 471/* "NFExists" (R): Nested Fault feature exists. */ 472#define MIPSNN_CFG5_NF_EXISTS __BIT(0) 473 474 475/* 476 * Values in PerfCntCrl Register (CP0 Register 25, Selects 0, 2, 4, 6) 477 */ 478 479/* "M" (R): next PerCntCtl register present. */ 480#define MIPSNN_PERFCTL_M __BIT(31) 481 482/* "W" (R): Width - is a 64-bit counter. */ 483#define MIPSNN_PERFCTL_W __BIT(30) 484 485/* "Impl" (RAZ): Impl - implementation dependent field. */ 486#define MIPSNN_PERFCTL_IMPL __BITS(29,25) 487 488/* "EC" (Z): Reserved for Virtualisation Mode. */ 489#define MIPSNN_PERFCTL_EC __BITS(24,23) 490 491/* "PCTD" (RW): Performance Counter Trace Disable. */ 492#define MIPSNN_PERFCTL_PCTD __BIT(15) 493 494/* 495 * "EVENT" (RW): Event number. Note: The MIPS32/MIPS64 PRA specs define 496 * EventExt from 14:11 and Event from 10:5. For ease of use, we define a 497 * single 10 bit Event field. 498 */ 499#define MIPSNN_PERFCTL_EVENT __BITS(14,5) 500 501/* "IE" (RW): Interrupt Enable. */ 502#define MIPSNN_PERFCTL_IE __BIT(4) 503 504/* "U" (RW): Enables event counting in user mode. */ 505#define MIPSNN_PERFCTL_U __BIT(3) 506 507/* "S" (RW): Enables event counting in supervisor mode. */ 508#define MIPSNN_PERFCTL_S __BIT(2) 509 510/* "K" (RW): Enables event counting in kernel mode. */ 511#define MIPSNN_PERFCTL_K __BIT(1) 512 513/* "EXL" (RW): Enables event counting when EXL bit in Status is one. */ 514#define MIPSNN_PERFCTL_EXL __BIT(0) 515 516 517/* 518 * Values in Configuration Register 6 (CP0 Register 16, Select 6) 519 * for RMI XLP processors 520 */ 521 522/* "CTLB_SIZE" (R): Number of Combined TLB entries - 1. */ 523#define MIPSNN_RMIXLP_CFG6_CTLB_SIZE_MASK 0xffff0000 524#define MIPSNN_RMIXLP_CFG6_CTLB_SIZE_SHIFT 16 525 526/* "VTLB_SIZE" (R): Number of Variable TLB entries - 1. */ 527#define MIPSNN_RMIXLP_CFG6_VTLB_SIZE_MASK 0x0000ffc0 528#define MIPSNN_RMIXLP_CFG6_VTLB_SIZE_SHIFT 6 529 530/* "ELVT" (RW): Enable Large Variable TLB. */ 531#define MIPSNN_RMIXLP_CFG6_ELVT 0x00000020 532 533/* "EPW" (RW): Enable PageWalker. */ 534#define MIPSNN_RMIXLP_CFG6_EPW 0x00000008 535 536/* "EFT" (RW): Enable Fixed TLB. */ 537#define MIPSNN_RMIXLP_CFG6_EFT 0x00000004 538 539/* "PWI" (R): PageWalker implemented. */ 540#define MIPSNN_RMIXLP_CFG6_PWI 0x00000001 541 542/* "FTI" (R): Fixed TLB implemented. */ 543#define MIPSNN_RMIXLP_CFG6_FTI 0x00000001 544 545/* 546 * Values in Configuration Register 7 (CP0 Register 16, Select 7) 547 * for RMI XLP processors 548 */ 549 550/* "LG" (RW): Small or Large Page. */ 551#define MIPSNN_RMIXLP_CFG7_LG_MASK __BIT(61) 552 553/* "MASKLG" (RW): large page size supported in CAM only. */ 554#define MIPSNN_RMIXLP_CFG7_MASKLG_MASK 0x0000ff00 555#define MIPSNN_RMIXLP_CFG7_MASKLG_SHIFT 8 556 557#define MIPSNN_RMIXLP_CFG7_MASKLG_4KB (0xff >> 8) 558#define MIPSNN_RMIXLP_CFG7_MASKLG_16KB (0xff >> 7) 559#define MIPSNN_RMIXLP_CFG7_MASKLG_64KB (0xff >> 6) 560#define MIPSNN_RMIXLP_CFG7_MASKLG_256KB (0xff >> 5) 561#define MIPSNN_RMIXLP_CFG7_MASKLG_1MB (0xff >> 4) 562#define MIPSNN_RMIXLP_CFG7_MASKLG_4MB (0xff >> 3) 563#define MIPSNN_RMIXLP_CFG7_MASKLG_16MB (0xff >> 2) 564#define MIPSNN_RMIXLP_CFG7_MASKLG_64MB (0xff >> 1) 565#define MIPSNN_RMIXLP_CFG7_MASKLG_256MB (0xff >> 0) 566 567/* "MASKSM" (RW): small page size supported in CAM/RAM. */ 568#define MIPSNN_RMIXLP_CFG7_MASKSM_MASK 0x000000ff 569#define MIPSNN_RMIXLP_CFG7_MASKSM_SHIFT 0 570 571#define MIPSNN_RMIXLP_CFG7_MASKSM_4KB (0xff >> 8) 572#define MIPSNN_RMIXLP_CFG7_MASKSM_16KB (0xff >> 7) 573#define MIPSNN_RMIXLP_CFG7_MASKSM_64KB (0xff >> 6) 574#define MIPSNN_RMIXLP_CFG7_MASKSM_256KB (0xff >> 5) 575#define MIPSNN_RMIXLP_CFG7_MASKSM_1MB (0xff >> 4) 576#define MIPSNN_RMIXLP_CFG7_MASKSM_4MB (0xff >> 3) 577#define MIPSNN_RMIXLP_CFG7_MASKSM_16MB (0xff >> 2) 578#define MIPSNN_RMIXLP_CFG7_MASKSM_64MB (0xff >> 1) 579#define MIPSNN_RMIXLP_CFG7_MASKSM_256MB (0xff >> 0) 580 581 582/* 583 * Values in Configuration Register 6 (CP0 Register 16, Select 6) 584 * for the MTI 74K and 1074K cores. 585 */ 586/* "SPCD" (R/W): Sleep state Perforance Counter Disable. */ 587#define MIPSNN_MTI_CFG6_SPCD __BIT(14) 588 589/* "SYND" (R/W): SYNonym tag update Disable. */ 590#define MIPSNN_MTI_CFG6_SYND __BIT(13) 591 592/* "IFUPerfCtl" (R/W): IFU Performance Control. */ 593#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_MASK __BIT(12:10) 594#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_STALL 0 595#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_JUMP 1 596#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_STALLED_INSN 2 597#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CACHE_MISPREDICTION 3 598#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CACHE_PREDICTION 4 599#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_BAD_JR_CACHE_ENTRY 5 600#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_UNIMPL 6 601#define MIPSNN_MTI_CFG6_IFU_PERF_CTL_CBRACH_TAKEN 7 602 603/* "NMRUP" (R): Most Recently Used JTLB Replacement scheme Present. */ 604#define MIPSNN_MTI_CFG6_NMRUP __BIT(9) /* 1: implemented */ 605 606/* "NMRUD" (R/W): NMRU Disable. */ 607#define MIPSNN_MTI_CFG6_NMRUD __BIT(8) /* 1: TLBWR is random */ 608 609/* "JRCP" (R): JR Cache Present. */ 610#define MIPSNN_MTI_CFG6_JRCP __BIT(1) /* 1: implemented */ 611 612/* "JRCD" (R/W): JR Cache prediction Disable. */ 613#define MIPSNN_MTI_CFG6_JRCD __BIT(0) /* 1: disabled */ 614 615 616/* 617 * Values in Configuration Register 7 (CP0 Register 16, Select 7) 618 * for the MTI 24K, 34K, 74K, 1004K, and 1074K cores 619 */ 620 621/* "WII" (R): Wait IE Ignore. */ 622#define MIPSNN_MTI_CFG7_WII __BIT(31) 623 624/* "FPFS" (R/W): Fast Prepare For Store (74K, 1074K) */ 625#define MIPSNN_MTI_CFG7_FPFS __BIT(30) 626 627/* "IHB" (R/W): Implicit HB (74K, 1074K) */ 628#define MIPSNN_MTI_CFG7_IHB __BIT(29) 629 630/* "FPR1" (R): Float Point Ratio 1 (74K, 1074K). */ 631#define MIPSNN_MTI_CFG7_FPR1 __BIT(28) /* 1: 3:2 */ 632 633/* "SEHB" (R/W): slow EHB (74K, 1074K) */ 634#define MIPSNN_MTI_CFG7_SEHB __BIT(27) 635 636/* "CP2IO" (R/W): Force COP2 data to be in-order (74K, 1074K) */ 637#define MIPSNN_MTI_CFG7_CP2IO __BIT(26) 638 639/* "IAGN" (R/W): Issue LSU-side instructions in program order (74K, 1074K) */ 640#define MIPSNN_MTI_CFG7_IAGN __BIT(25) 641 642/* "IAGN" (R/W): Issue LSU-side instructions in program order (74K, 1074K) */ 643#define MIPSNN_MTI_CFG7_IAGN __BIT(25) 644 645/* "IALU" (R/W): Issue ALU-side instructions in program order (74K, 1074K) */ 646#define MIPSNN_MTI_CFG7_IALU __BIT(24) 647 648/* "DGHR" (R/W): disable global history in branch prediction (74K, 1074K). */ 649#define MIPSNN_MTI_CFG7_DGHR __BIT(23) /* 1: disable */ 650 651/* "SG" (R/W): Single Graduation per cycle (74K, 1074K). */ 652#define MIPSNN_MTI_CFG7_SG __BIT(22) /* 1: no superscalar */ 653 654/* "SUI" (R/W): Strict Uncached Instruction (SUI) policy control (74K, 1074K). */ 655#define MIPSNN_MTI_CFG7_SUI __BIT(21) 656 657/* "NCWB" (R/W): Non-Choerent WriteBack (1004K). */ 658#define MIPSNN_MTI_CFG7_NCWB __BIT(20) 659 660/* "PCT" (R): Performance Counters per TC (34K, 1004K). */ 661#define MIPSNN_MTI_CFG7_PCT __BIT(19) 662 663/* "HCI" (R): Hardware Cache Initialization. */ 664#define MIPSNN_MTI_CFG7_HCI __BIT(18) 665 666/* "FPR" (R): Float Point Ratio. */ 667#define MIPSNN_MTI_CFG7_FPR0 __BIT(17) /* 1: half speed */ 668 669#define MIPSNN_MTI_CFG7_FPR_MASK (MIPSNN_MTI_CFG7_FPR1|MIPSNN_MTI_CFG7_FPR0) 670#define MIPSNN_MTI_CFG7_FPR_SHIFT 0 671#define MIPSNN_MTI_CFG7_FPR_1to1 0 672#define MIPSNN_MTI_CFG7_FPR_2to1 MIPSNN_MTI_CFG7_FPR0 673#define MIPSNN_MTI_CFG7_FPR_3to2 MIPSNN_MTI_CFG7_FPR1 674#define MIPSNN_MTI_CFG7_FPR_RESERVED MIPSNN_MTI_CFG7_FPR_MASK 675 676/* "AR" (R): Alias Removal. */ 677#define MIPSNN_MTI_CFG7_AR __BIT(16) /* 1: no virt aliases */ 678 679/* "PREF" (R/W): Instruction Prefetching (74K, 1074K). */ 680#define MIPSNN_MTI_CFG7_PREF_MASK __BITS(12,11) 681#define MIPSNN_MTI_CFG7_PREF_SHIFT 11 682#define MIPSNN_MTI_CFG7_PREF_DISABLE 0 683#define MIPSNN_MTI_CFG7_PREF_ONELINE 1 684#define MIPSNN_MTI_CFG7_PREF_RESERVED 2 685#define MIPSNN_MTI_CFG7_PREF_TWOLINES 3 686 687/* "IAR" (R): Instruction Alias Removal. */ 688#define MIPSNN_MTI_CFG7_IAR __BIT(10) /* 1: no virt aliases */ 689 690/* "IVA" (R or RW): Instruction Virtual Alias fix disable. */ 691#define MIPSNN_MTI_CFG7_IVA __BIT(9) /* 1: fix disable */ 692 693/* "ES" (RW): External Sync. */ 694#define MIPSNN_MTI_CFG7_ES __BIT(8) 695 696/* "BTLM" (RW): Block TC on Load Miss. */ 697#define MIPSNN_MTI_CFG7_BTLM __BIT(7) 698 699/* "CPOOO" (RW): Out-Of-Order on Coprocessor interfaces (COP0/COP1). */ 700#define MIPSNN_MTI_CFG7_CPOOO __BIT(6) /* 1: disable OOO */ 701 702/* "NBLSU" (RW): Non-Blocking LSU. (24K, 34K) */ 703#define MIPSNN_MTI_CFG7_NBLSU __BIT(5) /* 1: stalls pipeline */ 704 705/* "UBL" (RW): Uncached Loads Blocking. */ 706#define MIPSNN_MTI_CFG7_UBL __BIT(4) /* 1: blocking loads */ 707 708/* "BP" (RW): Branch Prediction. */ 709#define MIPSNN_MTI_CFG7_BP __BIT(3) /* 1: disabled */ 710 711/* "RPS" (RW): Return Prediction Stack. */ 712#define MIPSNN_MTI_CFG7_RPS __BIT(2) /* 1: disabled */ 713 714/* "BHT" (RW): Branch History Table. */ 715#define MIPSNN_MTI_CFG7_BHT __BIT(1) /* 1: disabled */ 716 717/* "SL" (RW): Scheduled Loads. */ 718#define MIPSNN_MTI_CFG7_SL __BIT(0) /* 1: load misses block */ 719