1/*	$NetBSD: octeon_gpioreg.h,v 1.2 2020/06/22 03:05:07 simonb Exp $	*/
2
3/*
4 * Copyright (c) 2007 Internet Initiative Japan, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * GPIO Registers
31 */
32
33#ifndef _OCTEON_GPIOREG_H_
34#define _OCTEON_GPIOREG_H_
35
36#define	GPIO_BIT_CFG0				0x0001070000000800ULL
37#define	GPIO_BIT_CFG1				0x0001070000000808ULL
38#define	GPIO_BIT_CFG2				0x0001070000000810ULL
39#define	GPIO_BIT_CFG3				0x0001070000000818ULL
40#define	GPIO_BIT_CFG4				0x0001070000000820ULL
41#define	GPIO_BIT_CFG5				0x0001070000000828ULL
42#define	GPIO_BIT_CFG6				0x0001070000000830ULL
43#define	GPIO_BIT_CFG7				0x0001070000000838ULL
44#define	GPIO_BIT_CFG8				0x0001070000000840ULL
45#define	GPIO_BIT_CFG9				0x0001070000000848ULL
46#define	GPIO_BIT_CFG10				0x0001070000000850ULL
47#define	GPIO_BIT_CFG11				0x0001070000000858ULL
48#define	GPIO_BIT_CFG12				0x0001070000000860ULL
49#define	GPIO_BIT_CFG13				0x0001070000000868ULL
50#define	GPIO_BIT_CFG14				0x0001070000000870ULL
51#define	GPIO_BIT_CFG15				0x0001070000000878ULL
52#define	GPIO_RX_DAT				0x0001070000000880ULL
53#define	GPIO_TX_SET				0x0001070000000888ULL
54#define	GPIO_TX_CLR				0x0001070000000890ULL
55#define	GPIO_INT_CLR				0x0001070000000898ULL
56#define	GPIO_DBG_ENA				0x00010700000008a0ULL
57#define	GPIO_BOOT_ENA				0x00010700000008a8ULL
58#define	GPIO_XBIT_CFG16				0x0001070000000900ULL
59#define	GPIO_XBIT_CFG17				0x0001070000000908ULL
60#define	GPIO_XBIT_CFG18				0x0001070000000910ULL
61#define	GPIO_XBIT_CFG19				0x0001070000000918ULL
62#define	GPIO_XBIT_CFG20				0x0001070000000920ULL
63#define	GPIO_XBIT_CFG21				0x0001070000000928ULL
64#define	GPIO_XBIT_CFG22				0x0001070000000930ULL
65#define	GPIO_XBIT_CFG23				0x0001070000000938ULL
66
67#define	GPIO_BIT_CFG_XXX_63_12			UINT64_C(0xfffffffffffff000)
68#define	GPIO_BIT_CFG_FIL_SEL			UINT64_C(0x0000000000000f00)
69#define	GPIO_BIT_CFG_FIL_CNT			UINT64_C(0x00000000000000f0)
70#define	GPIO_BIT_CFG_INT_TYPE			UINT64_C(0x0000000000000008)
71#define	GPIO_BIT_CFG_INT_EN			UINT64_C(0x0000000000000004)
72#define	GPIO_BIT_CFG_RX_XOR			UINT64_C(0x0000000000000002)
73#define	GPIO_BIT_CFG_TX_OE			UINT64_C(0x0000000000000001)
74
75/* XXX */
76
77/* ---- bus_space */
78
79#define	GPIO_BASE				0x0001070000000800ULL
80#define	GPIO_SIZE				0x0200
81
82#define	GPIO_BIT_CFG0_OFFSET			0x0000
83#define	GPIO_BIT_CFG1_OFFSET			0x0008
84#define	GPIO_BIT_CFG2_OFFSET			0x0010
85#define	GPIO_BIT_CFG3_OFFSET			0x0018
86#define	GPIO_BIT_CFG4_OFFSET			0x0020
87#define	GPIO_BIT_CFG5_OFFSET			0x0028
88#define	GPIO_BIT_CFG6_OFFSET			0x0030
89#define	GPIO_BIT_CFG7_OFFSET			0x0038
90#define	GPIO_BIT_CFG8_OFFSET			0x0040
91#define	GPIO_BIT_CFG9_OFFSET			0x0048
92#define	GPIO_BIT_CFG10_OFFSET			0x0050
93#define	GPIO_BIT_CFG11_OFFSET			0x0058
94#define	GPIO_BIT_CFG12_OFFSET			0x0060
95#define	GPIO_BIT_CFG13_OFFSET			0x0068
96#define	GPIO_BIT_CFG14_OFFSET			0x0070
97#define	GPIO_BIT_CFG15_OFFSET			0x0078
98#define	GPIO_RX_DAT_OFFSET			0x0080
99#define	GPIO_TX_SET_OFFSET			0x0088
100#define	GPIO_TX_CLR_OFFSET			0x0090
101#define	GPIO_INT_CLR_OFFSET			0x0098
102#define	GPIO_DBG_ENA_OFFSET			0x00a0
103#define	GPIO_BOOT_ENA_OFFSET			0x00a8
104#define	GPIO_XBIT_CFG16_OFFSET			0x0100
105#define	GPIO_XBIT_CFG17_OFFSET			0x0108
106#define	GPIO_XBIT_CFG18_OFFSET			0x0110
107#define	GPIO_XBIT_CFG19_OFFSET			0x0118
108#define	GPIO_XBIT_CFG20_OFFSET			0x0120
109#define	GPIO_XBIT_CFG21_OFFSET			0x0128
110#define	GPIO_XBIT_CFG22_OFFSET			0x0130
111#define	GPIO_XBIT_CFG23_OFFSET			0x0138
112
113#endif /* _OCTEON_GPIOREG_H_ */
114