1/* $NetBSD: octeon_dwctwo.c,v 1.15 2021/08/07 16:18:59 thorpej Exp $ */ 2 3/* 4 * Copyright (c) 2015 Masao Uebayashi <uebayasi@tombiinc.com> 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* 20 * Copyright (c) 2015 Internet Initiative Japan, Inc. 21 * All rights reserved. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in the 30 * documentation and/or other materials provided with the distribution. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 */ 44 45#include <sys/cdefs.h> 46__KERNEL_RCSID(0, "$NetBSD: octeon_dwctwo.c,v 1.15 2021/08/07 16:18:59 thorpej Exp $"); 47 48#include "opt_usb.h" 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/device.h> 53#include <sys/bus.h> 54#include <sys/cpu.h> 55#include <sys/workqueue.h> 56 57#include <dev/usb/usb.h> 58#include <dev/usb/usbdi.h> 59#include <dev/usb/usbdivar.h> 60#include <dev/usb/usb_mem.h> 61 62#include <mips/cavium/include/iobusvar.h> 63#include <mips/cavium/dev/octeon_ciureg.h> 64#include <mips/cavium/dev/octeon_usbnreg.h> 65#include <mips/cavium/dev/octeon_usbcreg.h> 66#include <mips/cavium/octeonvar.h> 67 68#include <dwc2/dwc2var.h> 69#include <dwc2/dwc2.h> 70#include "dwc2_core.h" 71 72struct octeon_dwc2_softc { 73 struct dwc2_softc sc_dwc2; 74 /* USBC bus space tag */ 75 struct mips_bus_space sc_dwc2_bust; 76 77 /* USBN bus space */ 78 bus_space_tag_t sc_bust; 79 bus_space_handle_t sc_regh; 80 bus_space_handle_t sc_reg2h; 81 82 void *sc_ih; 83}; 84 85static int octeon_dwc2_match(device_t, struct cfdata *, void *); 86static void octeon_dwc2_attach(device_t, device_t, void *); 87static uint32_t octeon_dwc2_rd_4(void *, bus_space_handle_t, bus_size_t); 88static void octeon_dwc2_wr_4(void *, bus_space_handle_t, bus_size_t, 89 uint32_t); 90static int octeon_dwc2_set_dma_addr(device_t, bus_addr_t, int); 91static void octeon_dwc2_reg_assert(struct octeon_dwc2_softc *, bus_size_t, 92 uint64_t); 93static void octeon_dwc2_reg_deassert(struct octeon_dwc2_softc *, bus_size_t, 94 uint64_t); 95static uint64_t octeon_dwc2_reg_rd(struct octeon_dwc2_softc *, bus_size_t); 96static void octeon_dwc2_reg_wr(struct octeon_dwc2_softc *, bus_size_t, 97 uint64_t); 98static void octeon_dwc2_reg2_wr(struct octeon_dwc2_softc *, bus_size_t, 99 uint64_t); 100 101static struct dwc2_core_params octeon_dwc2_params = { 102 .otg_cap = 2, /* 2 - No HNP/SRP capable */ 103 .otg_ver = 0, 104 .dma_enable = 1, 105 .dma_desc_enable = 0, 106 .speed = 0, /* 0 - High Speed */ 107 .enable_dynamic_fifo = 1, 108 .en_multiple_tx_fifo = 0, 109 .host_rx_fifo_size = 456, 110 .host_nperio_tx_fifo_size = 912, 111 .host_perio_tx_fifo_size = 256, 112 .max_transfer_size = 65535, 113 .max_packet_count = 511, 114 .host_channels = 8, 115 .phy_type = 1, /* UTMI */ 116 .phy_utmi_width = 16, /* 16 bits */ 117 .phy_ulpi_ddr = 0, 118 .phy_ulpi_ext_vbus = 0, 119 .i2c_enable = 0, 120 .ulpi_fs_ls = 0, 121 .host_support_fs_ls_low_power = 0, 122 .host_ls_low_power_phy_clk = 0, /* 48 MHz */ 123 .ts_dline = 0, 124 .reload_ctl = 0, 125 .ahbcfg = 0, /* XXX */ 126 .uframe_sched = 1, 127 .external_id_pin_ctl = -1, 128 .hibernation = -1, 129}; 130 131CFATTACH_DECL_NEW(octdwctwo, sizeof(struct octeon_dwc2_softc), 132 octeon_dwc2_match, octeon_dwc2_attach, NULL, NULL); 133 134static int 135octeon_dwc2_match(device_t parent, struct cfdata *cf, void *aux) 136{ 137 const mips_prid_t cpu_id = mips_options.mips_cpu_id; 138 struct iobus_attach_args *aa = aux; 139 140 if (strcmp(cf->cf_name, aa->aa_name) != 0) 141 return 0; 142 143 switch (MIPS_PRID_IMPL(cpu_id)) { 144 case MIPS_CN31XX: 145 case MIPS_CN30XX: 146 case MIPS_CN50XX: 147 return 1; 148 default: 149 return 0; 150 } 151} 152 153static void 154octeon_dwc2_attach(device_t parent, device_t self, void *aux) 155{ 156 struct octeon_dwc2_softc *sc = device_private(self); 157 struct iobus_attach_args *aa = aux; 158 uint64_t clk; 159 int status; 160 161 aprint_normal("\n"); 162 163 sc->sc_dwc2.sc_dev = self; 164 sc->sc_bust = aa->aa_bust; 165 166 sc->sc_dwc2_bust.bs_cookie = sc; 167 sc->sc_dwc2_bust.bs_map = aa->aa_bust->bs_map; 168 sc->sc_dwc2_bust.bs_unmap = aa->aa_bust->bs_unmap; 169 sc->sc_dwc2_bust.bs_r_4 = octeon_dwc2_rd_4; 170 sc->sc_dwc2_bust.bs_w_4 = octeon_dwc2_wr_4; 171 172 sc->sc_dwc2.sc_iot = &sc->sc_dwc2_bust; 173 sc->sc_dwc2.sc_bus.ub_dmatag = aa->aa_dmat; 174 sc->sc_dwc2.sc_params = &octeon_dwc2_params; 175 sc->sc_dwc2.sc_set_dma_addr = octeon_dwc2_set_dma_addr; 176 177 status = bus_space_map(sc->sc_dwc2.sc_iot, USBC_BASE, USBC_SIZE, 178 0, &sc->sc_dwc2.sc_ioh); 179 if (status != 0) 180 panic("can't map USBC space"); 181 182 status = bus_space_map(sc->sc_bust, USBN_BASE, USBN_SIZE, 183 0, &sc->sc_regh); 184 if (status != 0) 185 panic("can't map USBN space"); 186 187 status = bus_space_map(sc->sc_bust, USBN_2_BASE, USBN_2_SIZE, 188 0, &sc->sc_reg2h); 189 if (status != 0) 190 panic("can't map USBN_2 space"); 191 192 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 193 case MIPS_CN50XX: 194 /* 195 * 2. Configure the reference clock, PHY, and HCLK: 196 * a. Write USBN_CLK_CTL[POR] = 1 and 197 * USBN_CLK_CTL[HRST,PRST,HCLK_RST] = 0 198 */ 199 clk = octeon_dwc2_reg_rd(sc, USBN_CLK_CTL_OFFSET); 200 clk |= USBN_CLK_CTL_POR; 201 clk &= ~(USBN_CLK_CTL_HRST | USBN_CLK_CTL_PRST | 202 USBN_CLK_CTL_HCLK_RST | USBN_CLK_CTL_ENABLE); 203 /* 204 * b. Select the USB reference clock/crystal parameters by writing 205 * appropriate values to USBN_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]. 206 */ 207 /* XXX board specific */ 208 clk &= ~(USBN_CLK_CTL_P_C_SEL | USBN_CLK_CTL_P_RTYPE | 209 USBN_CLK_CTL_P_COM_ON); 210 /* 211 * c. Select the HCLK via writing USBN_CLK_CTL[DIVIDE, DIVIDE2] and 212 * setting USBN_CLK_CTL[ENABLE] = 1. 213 */ 214 /* XXX board specific */ 215 clk &= ~(USBN_CLK_CTL_DIVIDE | USBN_CLK_CTL_DIVIDE2); 216 clk |= __SHIFTIN(0x4, USBN_CLK_CTL_DIVIDE) | /* XXXXXX magic 0x4 */ 217 __SHIFTIN(0x0, USBN_CLK_CTL_DIVIDE2); 218 octeon_dwc2_reg_wr(sc, USBN_CLK_CTL_OFFSET, clk); 219 /* 220 * d. Write USBN_CLK_CTL[HCLK_RST] = 1. 221 */ 222 octeon_dwc2_reg_assert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_HCLK_RST); 223 /* 224 * e. Wait 64 core-clock cycles for HCLK to stabilize. 225 */ 226 delay(1); 227 break; 228 case MIPS_CN31XX: 229 case MIPS_CN30XX: 230 /* 231 * 2. If changing the HCLK divide value: 232 * a. write USBN_CLK_CTL[DIVIDE] with the new divide value. 233 */ 234 clk = octeon_dwc2_reg_rd(sc, USBN_CLK_CTL_OFFSET); 235 clk |= __SHIFTIN(0x4, USBN_CLK_CTL_DIVIDE); /* XXXXXX magic 0x4 */ 236 octeon_dwc2_reg_wr(sc, USBN_CLK_CTL_OFFSET, clk); 237 /* 238 * b. Wait 64 core-clock cycles for HCLK to stabilize. 239 */ 240 delay(1); 241 break; 242 default: 243 panic("unknown H/W type"); /* shouldn't get here */ 244 } 245 246 /* 247 * 3. Program the power-on reset field in the USBN clock-control register: 248 * USBN_CLK_CTL[POR] = 0 249 */ 250 octeon_dwc2_reg_deassert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_POR); 251 /* 252 * 4. Wait 40 us for PHY clock to start (CN3xxx) 253 * 4. Wait 1 ms for PHY clock to start (CN50xx) 254 */ 255 delay(1000); 256 257 /* 258 * 5. Program the Reset input from automatic test equipment field 259 * in the USBP control and status register: 260 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1 261 */ 262 octeon_dwc2_reg_assert(sc, USBN_USBP_CTL_STATUS_OFFSET, 263 USBN_USBP_CTL_STATUS_ATE_RESET); 264 /* 265 * 6. Wait 10 cycles. 266 */ 267 delay(1); 268 /* 269 * 7. Clear ATE_RESET field in the USBN clock-control register: 270 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0 271 */ 272 octeon_dwc2_reg_deassert(sc, USBN_USBP_CTL_STATUS_OFFSET, 273 USBN_USBP_CTL_STATUS_ATE_RESET); 274 /* 275 * 8. Program the PHY reset field in the USBN clock-control register: 276 * USBN_CLK_CTL[PRST] = 1 277 */ 278 octeon_dwc2_reg_assert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_PRST); 279 /* 280 * 9. Program the USBP control and status register to select host or device mode. 281 * USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for device 282 */ 283 octeon_dwc2_reg_deassert(sc, USBN_USBP_CTL_STATUS_OFFSET, 284 USBN_USBP_CTL_STATUS_HST_MODE); 285 /* 286 * 10. Wait 1 us. 287 */ 288 delay(1); 289 290 /* 291 * 11. Program the hreset_n field in the USBN clock-control register: 292 * USBN_CLK_CTL[HRST] = 1 293 */ 294 octeon_dwc2_reg_assert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_HRST); 295 296 delay(1); 297 298 /* Finally, enable clock */ 299 octeon_dwc2_reg_assert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_ENABLE); 300 301 delay(10); 302 303 status = dwc2_init(&sc->sc_dwc2); 304 if (status != 0) 305 panic("can't initialize dwc2, error=%d\n", status); 306 307 sc->sc_dwc2.sc_child = 308 config_found(sc->sc_dwc2.sc_dev, &sc->sc_dwc2.sc_bus, usbctlprint, 309 CFARGS_NONE); 310 311 sc->sc_ih = octeon_intr_establish(CIU_INT_USB, IPL_VM, dwc2_intr, sc); 312 if (sc->sc_ih == NULL) 313 panic("can't establish common interrupt\n"); 314} 315 316static uint32_t 317octeon_dwc2_rd_4(void *v, bus_space_handle_t h, bus_size_t off) 318{ 319 320 /* dwc2 uses little-endian addressing */ 321 return mips_lwu((h + off) ^ 4); 322} 323 324static void 325octeon_dwc2_wr_4(void *v, bus_space_handle_t h, bus_size_t off, 326 uint32_t val) 327{ 328 329 /* dwc2 uses little-endian addressing */ 330 mips_sw((h + off) ^ 4, val); 331} 332 333static int 334octeon_dwc2_set_dma_addr(device_t self, dma_addr_t dma_addr, int ch) 335{ 336 struct octeon_dwc2_softc *sc = device_private(self); 337 338 octeon_dwc2_reg2_wr(sc, 339 USBN_DMA0_INB_CHN0_OFFSET + ch * 0x8, dma_addr); 340 octeon_dwc2_reg2_wr(sc, 341 USBN_DMA0_OUTB_CHN0_OFFSET + ch * 0x8, dma_addr); 342 return 0; 343} 344 345static void 346octeon_dwc2_reg_assert(struct octeon_dwc2_softc *sc, bus_size_t offset, 347 uint64_t bits) 348{ 349 uint64_t value; 350 351 value = octeon_dwc2_reg_rd(sc, offset); 352 value |= bits; 353 octeon_dwc2_reg_wr(sc, offset, value); 354} 355 356static void 357octeon_dwc2_reg_deassert(struct octeon_dwc2_softc *sc, bus_size_t offset, 358 uint64_t bits) 359{ 360 uint64_t value; 361 362 value = octeon_dwc2_reg_rd(sc, offset); 363 value &= ~bits; 364 octeon_dwc2_reg_wr(sc, offset, value); 365} 366 367static uint64_t 368octeon_dwc2_reg_rd(struct octeon_dwc2_softc *sc, bus_size_t off) 369{ 370 return bus_space_read_8(sc->sc_bust, sc->sc_regh, off); 371} 372 373static void 374octeon_dwc2_reg_wr(struct octeon_dwc2_softc *sc, bus_size_t off, uint64_t val) 375{ 376 bus_space_write_8(sc->sc_bust, sc->sc_regh, off, val); 377 /* guarantee completion of the store operation on RSL registers*/ 378 bus_space_read_8(sc->sc_bust, sc->sc_regh, off); 379} 380 381static void 382octeon_dwc2_reg2_wr(struct octeon_dwc2_softc *sc, bus_size_t off, uint64_t val) 383{ 384 bus_space_write_8(sc->sc_bust, sc->sc_reg2h, off, val); 385 /* guarantee completion of the store operation on RSL registers*/ 386 bus_space_read_8(sc->sc_bust, sc->sc_reg2h, off); 387} 388