1/*	$NetBSD: octeon_ciureg.h,v 1.11 2020/07/20 17:56:13 jmcneill Exp $	*/
2
3/*
4 * Copyright (c) 2007 Internet Initiative Japan, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * CIU Registers
31 */
32
33#ifndef _OCTEON_CIUREG_H_
34#define _OCTEON_CIUREG_H_
35
36/* ---- register addresses */
37
38#define	CIU_INT0_SUM0				UINT64_C(0x0001070000000000)
39#define	CIU_INT1_SUM0				UINT64_C(0x0001070000000008)
40#define	CIU_INT2_SUM0				UINT64_C(0x0001070000000010)
41#define	CIU_INT3_SUM0				UINT64_C(0x0001070000000018)
42#define	CIU_IP2_SUM0(n)				(CIU_INT0_SUM0 + 0x10 * (n))
43#define	CIU_IP3_SUM0(n)				(CIU_INT1_SUM0 + 0x10 * (n))
44#define	CIU_INT32_SUM0				UINT64_C(0x0001070000000100)
45#define	CIU_INT_SUM1				UINT64_C(0x0001070000000108)
46#define	CIU_INT0_EN0				UINT64_C(0x0001070000000200)
47#define	CIU_INT1_EN0				UINT64_C(0x0001070000000210)
48#define	CIU_INT2_EN0				UINT64_C(0x0001070000000220)
49#define	CIU_INT3_EN0				UINT64_C(0x0001070000000230)
50#define	CIU_IP2_EN0(n)				(CIU_INT0_EN0 + 0x20 * (n))
51#define	CIU_IP3_EN0(n)				(CIU_INT1_EN0 + 0x20 * (n))
52#define	CIU_INT32_EN0				UINT64_C(0x0001070000000400)
53#define	CIU_INT0_EN1				UINT64_C(0x0001070000000208)
54#define	CIU_INT1_EN1				UINT64_C(0x0001070000000218)
55#define	CIU_INT2_EN1				UINT64_C(0x0001070000000228)
56#define	CIU_INT3_EN1				UINT64_C(0x0001070000000238)
57#define	CIU_IP2_EN1(n)				(CIU_INT0_EN1 + 0x20 * (n))
58#define	CIU_IP3_EN1(n)				(CIU_INT1_EN1 + 0x20 * (n))
59#define	CIU_INT32_EN1				UINT64_C(0x0001070000000408)
60#define	CIU_TIM0				UINT64_C(0x0001070000000480)
61#define	CIU_TIM1				UINT64_C(0x0001070000000488)
62#define	CIU_TIM2				UINT64_C(0x0001070000000490)
63#define	CIU_TIM3				UINT64_C(0x0001070000000498)
64#define	CIU_WDOG0				UINT64_C(0x0001070000000500)
65#define	CIU_WDOG(n)				(CIU_WDOG0 + (n) * 8)
66#define	CIU_PP_POKE0				UINT64_C(0x0001070000000580)
67#define	CIU_PP_POKE1				UINT64_C(0x0001070000000588)
68#define	CIU_PP_POKE(n)				(CIU_PP_POKE0 + (n) * 8)
69#define	CIU_MBOX_SET0				UINT64_C(0x0001070000000600)
70#define	CIU_MBOX_SET1				UINT64_C(0x0001070000000608)
71#define	CIU_MBOX_SET(n)				(CIU_MBOX_SET0 + (n) * 8)
72#define	CIU_MBOX_CLR0				UINT64_C(0x0001070000000680)
73#define	CIU_MBOX_CLR1				UINT64_C(0x0001070000000688)
74#define	CIU_MBOX_CLR(n)				(CIU_MBOX_CLR0 + (n) * 8)
75#define	CIU_PP_RST				UINT64_C(0x0001070000000700)
76#define	CIU_PP_DBG				UINT64_C(0x0001070000000708)
77#define	CIU_GSTOP				UINT64_C(0x0001070000000710)
78#define	CIU_NMI					UINT64_C(0x0001070000000718)
79#define	CIU_DINT				UINT64_C(0x0001070000000720)
80#define	CIU_FUSE				UINT64_C(0x0001070000000728)
81#define	CIU_BIST				UINT64_C(0x0001070000000730)
82#define	CIU_SOFT_BIST				UINT64_C(0x0001070000000738)
83#define	CIU_SOFT_RST				UINT64_C(0x0001070000000740)
84#define	CIU_SOFT_PRST				UINT64_C(0x0001070000000748)
85#define	CIU_PCI_INTA				UINT64_C(0x0001070000000750)
86#define	CIU_INT4_SUM0				UINT64_C(0x0001070000000c00)
87#define	CIU_INT4_SUM1				UINT64_C(0x0001070000000c08)
88#define	CIU_IP4_SUM0(n)				(CIU_INT4_SUM0 + 0x8 * (n))
89#define	CIU_INT4_EN00				UINT64_C(0x0001070000000c80)
90#define	CIU_INT4_EN01				UINT64_C(0x0001070000000c88)
91#define	CIU_INT4_EN10				UINT64_C(0x0001070000000c90)
92#define	CIU_INT4_EN11				UINT64_C(0x0001070000000c98)
93#define	CIU_IP4_EN0(n)				(CIU_INT4_EN00 + 0x10 * (n))
94#define	CIU_IP4_EN1(n)				(CIU_INT4_EN01 + 0x10 * (n))
95
96#define	CIU_BASE				UINT64_C(0x0001070000000000)
97
98#define	CIU_INT0_SUM0_OFFSET			0x0000
99#define	CIU_INT1_SUM0_OFFSET			0x0008
100#define	CIU_INT2_SUM0_OFFSET			0x0010
101#define	CIU_INT3_SUM0_OFFSET			0x0018
102#define	CIU_INT32_SUM0_OFFSET			0x0100
103#define	CIU_INT_SUM1_OFFSET			0x0108
104#define	CIU_INT0_EN0_OFFSET			0x0200
105#define	CIU_INT1_EN0_OFFSET			0x0210
106#define	CIU_INT2_EN0_OFFSET			0x0220
107#define	CIU_INT3_EN0_OFFSET			0x0230
108#define	CIU_INT32_EN0_OFFSET			0x0400
109#define	CIU_INT0_EN1_OFFSET			0x0208
110#define	CIU_INT1_EN1_OFFSET			0x0218
111#define	CIU_INT2_EN1_OFFSET			0x0228
112#define	CIU_INT3_EN1_OFFSET			0x0238
113#define	CIU_INT32_EN1_OFFSET			0x0408
114#define	CIU_TIM0_OFFSET				0x0480
115#define	CIU_TIM1_OFFSET				0x0488
116#define	CIU_TIM2_OFFSET				0x0490
117#define	CIU_TIM3_OFFSET				0x0498
118#define	CIU_WDOG0_OFFSET			0x0500
119#define	CIU_WDOG1_OFFSET			0x0508
120#define	CIU_PP_POKE0_OFFSET			0x0580
121#define	CIU_PP_POKE1_OFFSET			0x0588
122#define	CIU_MBOX_SET0_OFFSET			0x0600
123#define	CIU_MBOX_SET1_OFFSET			0x0608
124#define	CIU_MBOX_CLR0_OFFSET			0x0680
125#define	CIU_MBOX_CLR1_OFFSET			0x0688
126#define	CIU_PP_RST_OFFSET			0x0700
127#define	CIU_PP_DBG_OFFSET			0x0708
128#define	CIU_GSTOP_OFFSET			0x0710
129#define	CIU_NMI_OFFSET				0x0718
130#define	CIU_DINT_OFFSET				0x0720
131#define	CIU_FUSE_OFFSET				0x0728
132#define	CIU_BIST_OFFSET				0x0730
133#define	CIU_SOFT_BIST_OFFSET			0x0738
134#define	CIU_SOFT_RST_OFFSET			0x0740
135#define	CIU_SOFT_PRST_OFFSET			0x0748
136#define	CIU_PCI_INTA_OFFSET			0x0750
137
138/* ---- register bits */
139
140/* interrupt numbers */
141
142#define	CIU_INT_BOOTDMA				63
143#define	CIU_INT_MII				62
144#define	CIU_INT_IPDPPTHR			61
145#define	CIU_INT_POWIQ				60
146#define	CIU_INT_TWSI2				59
147#define	CIU_INT_MPI				58
148#define	CIU_INT_PCM				57
149#define	CIU_INT_USB				56
150#define	CIU_INT_TIMER_3				55
151#define	CIU_INT_TIMER_2				54
152#define	CIU_INT_TIMER_1				53
153#define	CIU_INT_TIMER_0				52
154#define	CIU_INT_KEY_ZERO			51
155#define	CIU_INT_IPD_DRP				50
156#define	CIU_INT_GMX_DRP2			49
157#define	CIU_INT_GMX_DRP				48
158#define	CIU_INT_TRACE				47
159#define	CIU_INT_RML				46
160#define	CIU_INT_TWSI				45
161#define	CIU_INT_WDOG_SUM			44
162#define	CIU_INT_PCI_MSI_63_48			43
163#define	CIU_INT_PCI_MSI_47_32			42
164#define	CIU_INT_PCI_MSI_31_16			41
165#define	CIU_INT_PCI_MSI_15_0			40
166#define	CIU_INT_PCI_INT_D			39
167#define	CIU_INT_PCI_INT_C			38
168#define	CIU_INT_PCI_INT_B			37
169#define	CIU_INT_PCI_INT_A			36
170#define	CIU_INT_UART_1				35
171#define	CIU_INT_UART_0				34
172#define	CIU_INT_MBOX_31_16			33
173#define	CIU_INT_MBOX_15_0			32
174#define	CIU_INT_GPIO_15				31
175#define	CIU_INT_GPIO_14				30
176#define	CIU_INT_GPIO_13				29
177#define	CIU_INT_GPIO_12				28
178#define	CIU_INT_GPIO_11				27
179#define	CIU_INT_GPIO_10				26
180#define	CIU_INT_GPIO_9				25
181#define	CIU_INT_GPIO_8				24
182#define	CIU_INT_GPIO_7				23
183#define	CIU_INT_GPIO_6				22
184#define	CIU_INT_GPIO_5				21
185#define	CIU_INT_GPIO_4				20
186#define	CIU_INT_GPIO_3				19
187#define	CIU_INT_GPIO_2				18
188#define	CIU_INT_GPIO_1				17
189#define	CIU_INT_GPIO_0				16
190#define	CIU_INT_WORKQ_15			15
191#define	CIU_INT_WORKQ_14			14
192#define	CIU_INT_WORKQ_13			13
193#define	CIU_INT_WORKQ_12			12
194#define	CIU_INT_WORKQ_11			11
195#define	CIU_INT_WORKQ_10			10
196#define	CIU_INT_WORKQ_9				 9
197#define	CIU_INT_WORKQ_8				 8
198#define	CIU_INT_WORKQ_7				 7
199#define	CIU_INT_WORKQ_6				 6
200#define	CIU_INT_WORKQ_5				 5
201#define	CIU_INT_WORKQ_4				 4
202#define	CIU_INT_WORKQ_3				 3
203#define	CIU_INT_WORKQ_2				 2
204#define	CIU_INT_WORKQ_1				 1
205#define	CIU_INT_WORKQ_0				 0
206
207#define	CUI_INT_WDOG_15				 15
208#define	CUI_INT_WDOG_14				 14
209#define	CUI_INT_WDOG_13				 13
210#define	CUI_INT_WDOG_12				 12
211#define	CUI_INT_WDOG_11				 11
212#define	CUI_INT_WDOG_10				 10
213#define	CUI_INT_WDOG_9				  9
214#define	CUI_INT_WDOG_8				  8
215#define	CUI_INT_WDOG_7				  7
216#define	CUI_INT_WDOG_6				  6
217#define	CUI_INT_WDOG_5				  5
218#define	CUI_INT_WDOG_4				  4
219#define	CUI_INT_WDOG_3				  3
220#define	CUI_INT_WDOG_2				  2
221#define	CUI_INT_WDOG_1				  1
222#define	CUI_INT_WDOG_0				  0
223
224#define	CIU_TIMX_XXX_63_37			UINT64_C(0xffffffe000000000)
225#define	CIU_TIMX_ONE_SHOT			UINT64_C(0x0000001000000000)
226#define	CIU_TIMX_LEN				UINT64_C(0x0000000fffffffff)
227
228#define	CIU_WDOGX_XXX_63_46			UINT64_C(0xffffc00000000000)
229#define	CIU_WDOGX_GSTOPEN			UINT64_C(0x0000200000000000)
230#define	CIU_WDOGX_DSTOP				UINT64_C(0x0000100000000000)
231#define	CIU_WDOGX_CNT				UINT64_C(0x00000ffffff00000)
232#define	CIU_WDOGX_LEN				UINT64_C(0x00000000000ffff0)
233#define	CIU_WDOGX_STATE				UINT64_C(0x000000000000000c)
234#define	CIU_WDOGX_MODE				UINT64_C(0x0000000000000003)
235#define	  CIU_WDOGX_MODE_OFF			  0
236#define	  CIU_WDOGX_MODE_INTR			  1
237#define	  CIU_WDOGX_MODE_INTR_NMI		  2
238#define	  CIU_WDOGX_MODE_INTR_NMI_SOFT		  3
239
240#define	CIU_PP_POKEX_XXX_63_0			UINT64_C(0xffffffffffffffff)
241
242#define	CIU_MBOX_SETX_XXX_63_32			UINT64_C(0xffffffff00000000)
243#define	CIU_MBOX_SETX_SET			UINT64_C(0x00000000ffffffff)
244
245#define	CIU_MBOX_CLRX_XXX_63_32			UINT64_C(0xffffffff00000000)
246#define	CIU_MBOX_CLRX_CLR			UINT64_C(0x00000000ffffffff)
247
248#define	CIU_PP_RST_RST				UINT64_C(0x0000ffffffffffff)
249#define	CIU_PP_RST_RST0				UINT64_C(0x0000000000000001)
250
251#define	CIU_PP_DBG_PPDBG			UINT64_C(0x0000ffffffffffff)
252
253#define	CIU_GSTOP_XXX_63_1			UINT64_C(0xfffffffffffffffe)
254#define	CIU_GSTOP_GSTOP				UINT64_C(0x0000000000000001)
255
256#define	CIU_NMI_NMI				UINT64_C(0x0000ffffffffffff)
257
258#define	CIU_DINT_DINT				UINT64_C(0x0000ffffffffffff)
259
260#define	CIU_FUSE_FUSE				UINT64_C(0x0000ffffffffffff)
261
262#define	CIU_BIST_BIST				UINT64_C(0x0000ffffffffffff)
263
264#define	CIU_SOFT_BIST_XXX_63_1			UINT64_C(0xfffffffffffffffe)
265#define	CIU_SOFT_BIST_SOFT_BIST			UINT64_C(0x0000000000000001)
266
267#define	CIU_SOFT_RST_XXX_63_1			UINT64_C(0xfffffffffffffffe)
268#define	CIU_SOFT_RST_SOFT_RST			UINT64_C(0x0000000000000001)
269
270#define	CIU_SOFT_PRST_XXX_63_4			UINT64_C(0xfffffffffffffff8)
271#define	CIU_SOFT_PRST_HOST64			UINT64_C(0x0000000000000004)
272#define	CIU_SOFT_PRST_NPI			UINT64_C(0x0000000000000002)
273#define	CIU_SOFT_PRST_SOFT_PRST			UINT64_C(0x0000000000000001)
274
275#define	CIU_PCI_INTA_XXX_63_2			UINT64_C(0xfffffffffffffffc)
276#define	CIU_PCI_INTA_INT			UINT64_C(0x0000000000000003)
277
278#endif /* _OCTEON_CIUREG_H_ */
279