1/* $NetBSD: octeon_cib.c,v 1.7 2021/05/05 06:47:29 simonb Exp $ */
2
3/*-
4 * Copyright (c) 2020 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include "opt_multiprocessor.h"
30
31#include <sys/cdefs.h>
32__KERNEL_RCSID(0, "$NetBSD: octeon_cib.c,v 1.7 2021/05/05 06:47:29 simonb Exp $");
33
34#include <sys/param.h>
35#include <sys/bus.h>
36#include <sys/device.h>
37#include <sys/intr.h>
38#include <sys/systm.h>
39#include <sys/kernel.h>
40#include <sys/kmem.h>
41
42#include <dev/fdt/fdtvar.h>
43
44#include <arch/mips/cavium/octeonvar.h>
45
46static int	octeon_cib_match(device_t, cfdata_t, void *);
47static void	octeon_cib_attach(device_t, device_t, void *);
48
49static void *	octeon_cib_establish(device_t, u_int *, int, int,
50		    int (*)(void *), void *, const char *);
51static void	octeon_cib_disestablish(device_t, void *);
52static bool	octeon_cib_intrstr(device_t, u_int *, char *, size_t);
53
54static int	octeon_cib_intr(void *);
55
56static struct fdtbus_interrupt_controller_func octeon_cib_funcs = {
57	.establish = octeon_cib_establish,
58	.disestablish = octeon_cib_disestablish,
59	.intrstr = octeon_cib_intrstr
60};
61
62struct octeon_cib_intr {
63	bool			ih_mpsafe;
64	int			ih_type;
65	int			(*ih_func)(void *);
66	void			*ih_arg;
67	uint64_t		ih_mask;
68};
69
70struct octeon_cib_softc {
71	device_t		sc_dev;
72	int			sc_phandle;
73	bus_space_tag_t		sc_bst;
74	bus_space_handle_t	sc_bsh_raw;
75	bus_space_handle_t	sc_bsh_en;
76
77	struct octeon_cib_intr	*sc_intr;
78	u_int			sc_nintr;
79};
80
81#define	CIB_READ_RAW(sc)		\
82	bus_space_read_8((sc)->sc_bst, (sc)->sc_bsh_raw, 0)
83#define	CIB_WRITE_RAW(sc, val)		\
84	bus_space_write_8((sc)->sc_bst, (sc)->sc_bsh_raw, 0, (val))
85#define	CIB_READ_EN(sc)			\
86	bus_space_read_8((sc)->sc_bst, (sc)->sc_bsh_en, 0)
87#define	CIB_WRITE_EN(sc, val)		\
88	bus_space_write_8((sc)->sc_bst, (sc)->sc_bsh_en, 0, (val))
89
90CFATTACH_DECL_NEW(octcib, sizeof(struct octeon_cib_softc),
91	octeon_cib_match, octeon_cib_attach, NULL, NULL);
92
93static const struct device_compatible_entry compat_data[] = {
94	{ .compat = "cavium,octeon-7130-cib" },
95	DEVICE_COMPAT_EOL
96};
97
98static int
99octeon_cib_match(device_t parent, cfdata_t cf, void *aux)
100{
101	struct fdt_attach_args * const faa = aux;
102
103	return of_compatible_match(faa->faa_phandle, compat_data);
104}
105
106static void
107octeon_cib_attach(device_t parent, device_t self, void *aux)
108{
109	struct octeon_cib_softc * const sc = device_private(self);
110	struct fdt_attach_args * const faa = aux;
111	const int phandle = faa->faa_phandle;
112	char intrstr[128];
113	bus_addr_t addr;
114	bus_size_t size;
115	u_int max_bits;
116	int error;
117	void *ih;
118
119	sc->sc_dev = self;
120	sc->sc_phandle = phandle;
121	sc->sc_bst = faa->faa_bst;
122
123	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 ||
124	    bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_raw) != 0) {
125		aprint_error(": couldn't map RAW register\n");
126		return;
127	}
128	if (fdtbus_get_reg(phandle, 1, &addr, &size) != 0 ||
129	    bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_en) != 0) {
130		aprint_error(": couldn't map EN register\n");
131		return;
132	}
133
134	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
135		aprint_error(": failed to decode interrupt\n");
136		return;
137	}
138
139	if (of_getprop_uint32(phandle, "cavium,max-bits", &max_bits) != 0) {
140		aprint_error(": missing 'cavium,max-bits' property\n");
141		return;
142	}
143	if (max_bits == 0 || max_bits > 64) {
144		aprint_error(": 'cavium,max-bits' value out of range\n");
145		return;
146	}
147
148	sc->sc_intr = kmem_zalloc(sizeof(*sc->sc_intr) * max_bits, KM_SLEEP);
149	sc->sc_nintr = max_bits;
150
151	error = fdtbus_register_interrupt_controller(self, phandle,
152	    &octeon_cib_funcs);
153	if (error != 0) {
154		aprint_error(": couldn't register with fdtbus: %d\n", error);
155		return;
156	}
157
158	aprint_naive("\n");
159	aprint_normal(": CIB\n");
160
161	CIB_WRITE_EN(sc, 0);
162	CIB_WRITE_RAW(sc, ~0ULL);
163
164	ih = fdtbus_intr_establish(phandle, 0, IPL_SCHED, FDT_INTR_MPSAFE,
165	    octeon_cib_intr, sc);
166	if (ih == NULL) {
167		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
168		    intrstr);
169		return;
170	}
171	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
172}
173
174static void *
175octeon_cib_establish(device_t dev, u_int *specifier, int ipl, int flags,
176    int (*func)(void *), void *arg, const char *xname)
177{
178	struct octeon_cib_softc * const sc = device_private(dev);
179	struct octeon_cib_intr *ih;
180	uint64_t val;
181
182	/* 1st cell is the bit number in the CIB* registers */
183	/* 2nd cell is the triggering setting */
184	const int bit = be32toh(specifier[0]);
185	const int type = (be32toh(specifier[1]) & 0x3) ? IST_EDGE : IST_LEVEL;
186
187	if (bit > sc->sc_nintr) {
188		aprint_error_dev(dev, "bit %d out of range\n", bit);
189		return NULL;
190	}
191
192	ih = &sc->sc_intr[bit];
193	ih->ih_mpsafe = (flags & FDT_INTR_MPSAFE) != 0;
194	ih->ih_type = type;
195	ih->ih_func = func;
196	ih->ih_arg = arg;
197	ih->ih_mask = __BIT(bit);
198
199	val = CIB_READ_EN(sc);
200	val |= ih->ih_mask;
201	CIB_WRITE_EN(sc, val);
202
203	return ih;
204}
205
206static void
207octeon_cib_disestablish(device_t dev, void *ih_cookie)
208{
209	struct octeon_cib_softc * const sc = device_private(dev);
210	struct octeon_cib_intr *ih = ih_cookie;
211	uint64_t val;
212
213	val = CIB_READ_EN(sc);
214	val &= ~ih->ih_mask;
215	CIB_WRITE_EN(sc, val);
216}
217
218static bool
219octeon_cib_intrstr(device_t dev, u_int *specifier, char *buf,
220    size_t buflen)
221{
222	/* 1st cell is the bit number in the CIB* registers */
223	const int bit = be32toh(specifier[0]);
224
225	snprintf(buf, buflen, "%s intr %d", device_xname(dev), bit);
226
227	return true;
228}
229
230static int
231octeon_cib_intr(void *priv)
232{
233	struct octeon_cib_softc * const sc = priv;
234	struct octeon_cib_intr *ih;
235	uint64_t pend;
236	int n, rv = 0;
237
238	pend = CIB_READ_RAW(sc);
239	pend &= CIB_READ_EN(sc);
240
241	while ((n = ffs64(pend)) != 0) {
242		ih = &sc->sc_intr[n - 1];
243		KASSERT(ih->ih_mask == __BIT(n - 1));
244
245		if (ih->ih_type == IST_EDGE)
246			CIB_WRITE_RAW(sc, ih->ih_mask);	/* ack */
247
248#ifdef MULTIPROCESSOR
249		if (!ih->ih_mpsafe) {
250			KERNEL_LOCK(1, NULL);
251			rv |= ih->ih_func(ih->ih_arg);
252			KERNEL_UNLOCK_ONE(NULL);
253		} else
254#endif
255			rv |= ih->ih_func(ih->ih_arg);
256
257		pend &= ~ih->ih_mask;
258	}
259
260	return rv;
261}
262