1/* $NetBSD: aureg.h,v 1.9 2006/02/09 01:08:40 gdamore Exp $ */ 2 3/* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#ifndef _MIPS_ALCHEMY_AC97REG_H 39#define _MIPS_ALCHEMY_AC97REG_H 40 41/* ********************************************************************* 42 * Naming schemes for constants in these files: 43 * 44 * M_xxx MASK constant (identifies bits in a register). 45 * For multi-bit fields, all bits in the field will 46 * be set. 47 * 48 * K_xxx "Code" constant (value for data in a multi-bit 49 * field). The value is right justified. 50 * 51 * V_xxx "Value" constant. This is the same as the 52 * corresponding "K_xxx" constant, except it is 53 * shifted to the correct position in the register. 54 * 55 * S_xxx SHIFT constant. This is the number of bits that 56 * a field value (code) needs to be shifted 57 * (towards the left) to put the value in the right 58 * position for the register. 59 * 60 * A_xxx ADDRESS constant. This will be a physical 61 * address. Use the MIPS_PHYS_TO_KSEG1 macro to 62 * generate a K1SEG address. 63 * 64 * R_xxx RELATIVE offset constant. This is an offset from 65 * an A_xxx constant (usually the first register in 66 * a group). 67 * 68 * G_xxx(X) GET value. This macro obtains a multi-bit field 69 * from a register, masks it, and shifts it to 70 * the bottom of the register (retrieving a K_xxx 71 * value, for example). 72 * 73 * V_xxx(X) VALUE. This macro computes the value of a 74 * K_xxx constant shifted to the correct position 75 * in the register. 76 ********************************************************************* */ 77 78#if !defined(__ASSEMBLER__) 79#define _MAKE64(x) ((uint64_t)(x)) 80#define _MAKE32(x) ((uint32_t)(x)) 81#else 82#define _MAKE64(x) (x) 83#define _MAKE32(x) (x) 84#endif 85 86/* Make a mask for 1 bit at position 'n' */ 87#define _MAKEMASK1_64(n) (_MAKE64(1) << _MAKE64(n)) 88#define _MAKEMASK1_32(n) (_MAKE32(1) << _MAKE32(n)) 89 90/* Make a mask for 'v' bits at position 'n' */ 91#define _MAKEMASK_64(v,n) (_MAKE64((_MAKE64(1)<<(v))-1) << _MAKE64(n)) 92#define _MAKEMASK_32(v,n) (_MAKE32((_MAKE32(1)<<(v))-1) << _MAKE32(n)) 93 94/* Make a value at 'v' at bit position 'n' */ 95#define _MAKEVALUE_64(v,n) (_MAKE64(v) << _MAKE64(n)) 96#define _MAKEVALUE_32(v,n) (_MAKE32(v) << _MAKE32(n)) 97 98#define _GETVALUE_64(v,n,m) ((_MAKE64(v) & _MAKE64(m)) >> _MAKE64(n)) 99#define _GETVALUE_32(v,n,m) ((_MAKE32(v) & _MAKE32(m)) >> _MAKE32(n)) 100 101/******************** AC97 Controller registers *********************/ 102 103#define AC97_CONFIG 0x00 104 105#define M_AC97CFG_RS _MAKEMASK1_32(0) 106#define M_AC97CFG_SN _MAKEMASK1_32(1) 107#define M_AC97CFG_SG _MAKEMASK1_32(2) 108 109#define S_AC97CFG_XS _MAKE32(12) 110#define M_AC97CFG_XS _MAKEMASK_32(10) 111#define V_AC97CFG_XS(x) _MAKEVALUE_32(x, S_AC97CFG_XS) 112#define G_AC97CFG_XS(x) _GETVALUE_32(x, S_AC97CFG_XS, M_AC97CFG_XS) 113 114#define S_AC97CFG_RC _MAKE32(12) 115#define M_AC97CFG_RC _MAKEMASK_32(10) 116#define V_AC97CFG_RC(x) _MAKEVALUE_32(x, S_AC97CFG_RC) 117#define G_AC97CFG_RC(x) _GETVALUE_32(x, S_AC97CFG_RC, M_AC97CFG_RC) 118 119#define AC97_STATUS 0x04 120 121#define M_AC97STAT_RF _MAKEMASK1_32(0) 122#define M_AC97STAT_RE _MAKEMASK1_32(1) 123#define M_AC97STAT_TF _MAKEMASK1_32(3) 124#define M_AC97STAT_TE _MAKEMASK1_32(4) 125#define M_AC97STAT_CP _MAKEMASK1_32(6) 126#define M_AC97STAT_RD _MAKEMASK1_32(7) 127#define M_AC97STAT_RO _MAKEMASK1_32(8) 128#define M_AC97STAT_RU _MAKEMASK1_32(9) 129#define M_AC97STAT_XO _MAKEMASK1_32(10) 130#define M_AC97STAT_XU _MAKEMASK1_32(11) 131 132#define AC97_DATA 0x08 133 134#define S_AC97DATA_DATA _MAKE32(0) 135#define M_AC97DATA_DATA _MAKEMASK_32(16) 136#define V_AC97DATA_DATA(x) _MAKEVALUE_32(x, S_AC97DATA_DATA) 137#define G_AC97DATA_DATA(x) _GETVALUE_32(x, S_AC97DATA_DATA, M_AC97DATA_DATA) 138 139#define AC97_COMMAND 0x0c 140 141#define S_AC97CMD_INDEX _MAKE32(0) 142#define M_AC97CMD_INDEX _MAKEMASK_32(7) 143#define V_AC97CMD_INDEX(x) _MAKEVALUE_32(x, S_AC97CMD_INDEX) 144#define G_AC97CMD_INDEX(x) _GETVALUE_32(x, S_AC97CMD_INDEX, M_AC97CMD_INDEX) 145 146#define M_AC97CMD_RW _MAKEMASK1_32(7) 147 148#define S_AC97CMD_DATA _MAKE32(16) 149#define M_AC97CMD_DATA _MAKEMASK_32(16) 150#define V_AC97CMD_DATA(x) _MAKEVALUE_32(x, S_AC97CMD_DATA) 151#define G_AC97CMD_DATA(x) _GETVALUE_32(x, S_AC97CMD_DATA, M_AC97CMD_DATA) 152 153#define AC97_COMMAND_RESPONSE 0x0c 154 155#define S_AC97CMDRESP_DATA _MAKE32(0) 156#define M_AC97CMDRESP_DATA _MAKEMASK_32(16) 157#define V_AC97CMDRESP_DATA(x) _MAKEVALUE_32(x, S_AC97CMDRESP_DATA) 158#define G_AC97CMDRESP_DATA(x) _GETVALUE_32(x, S_AC97CMDRESP_DATA, M_AC97CMDRESP_DATA) 159 160#define AC97_ENABLE 0x10 161 162#define M_AC97EN_CE _MAKEMASK1_32(0) 163#define M_AC97EN_D _MAKEMASK1_32(1) 164 165#define AC97_SIZE 0x14 /* size of register set */ 166 167#endif /* _MIPS_ALCHEMY_AC97REG_H */ 168