1/*	$NetBSD: interrupts.c,v 1.10 2023/12/20 15:29:05 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2007 Michael Lorenz
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: interrupts.c,v 1.10 2023/12/20 15:29:05 thorpej Exp $");
31
32#include "opt_multiprocessor.h"
33
34#include <sys/param.h>
35#include <sys/kernel.h>
36
37#include <prop/proplib.h>
38
39#include <machine/intr.h>
40#include <machine/autoconf.h>
41#include <powerpc/pic/picvar.h>
42#include <powerpc/pic/ipivar.h>
43#include <dev/ofw/openfirm.h>
44#include <powerpc/oea/cpufeat.h>
45
46#include "opt_interrupt.h"
47#include "pic_openpic.h"
48#include "pic_ohare.h"
49#include "pic_heathrow.h"
50#include "pic_u3_ht.h"
51#include "opt_ipi.h"
52#include "ipi_openpic.h"
53#include "ipi_hammerhead.h"
54
55#if NPIC_OPENPIC > 0
56static int init_openpic(int);
57
58const char *compat[] = {
59	"chrp,open-pic",
60	"open-pic",
61	"openpic",
62	NULL
63};
64
65static int
66init_openpic(int pass_through)
67{
68	uint32_t reg[5];
69	uint32_t obio_base, pic_base;
70	int      pic, macio;
71
72	macio = OF_finddevice("/pci/mac-io");
73	if (macio == -1)
74		macio = OF_finddevice("mac-io");
75	if (macio == -1)
76		macio = OF_finddevice("/ht/pci/mac-io");
77	if (macio == -1)
78		return FALSE;
79
80	aprint_debug("macio: %08x\n", macio);
81
82	pic = OF_child(macio);
83	while ((pic != 0) && !of_compatible(pic, compat))
84		pic = OF_peer(pic);
85
86	aprint_debug("pic: %08x\n", pic);
87	if ((pic == -1) || (pic == 0))
88		return FALSE;
89
90	if (OF_getprop(macio, "assigned-addresses", reg, sizeof(reg)) != 20)
91		return FALSE;
92
93	obio_base = reg[2];
94	aprint_debug("obio-base: %08x\n", obio_base);
95
96	if (OF_getprop(pic, "reg", reg, 8) < 8)
97		return FALSE;
98
99	pic_base = obio_base + reg[0];
100	aprint_debug("pic-base: %08x\n", pic_base);
101
102	aprint_normal("found openpic PIC at %08x\n", pic_base);
103	setup_openpic(oea_mapiodev(pic_base, 0x40000), pass_through);
104
105	return TRUE;
106}
107
108#endif /* NPIC_OPENPIC > 0 */
109
110/*
111 * look for supported interrupt controllers
112 * there are several possible cases:
113 * - Ohare and Grand Central models have the same interrupt controller, Ohare
114 *   can have a 2nd cascaded one ( Powerbook 3400c with ethernet for example )
115 * - Heathrow is more or less Ohare with all the registers doubled to allow 64
116 *   IRQs
117 * - openpic covers all OpenPICs built into various mac-io found in some G3,
118 *   all G4 and most G5 models
119 * - u3_ht is an OpenPIC built into the CPC 9x5 bridges / memory controllers
120 *   found in G5s, it's got enough quirks to require its own driver. Some
121 *   models have both openpic and u3_ht, on those openpic handles IPIs and
122 *   normal IRQs while the u3_ht is cascaded and can be used for MSI. On G5s
123 *   that have no openpic the u3_ht handles all interrupts, IPIs and MSI
124 */
125void
126init_interrupt(void)
127{
128	int ok = 0;
129
130	pic_init();
131#if NPIC_OHARE > 0
132	if (init_ohare())
133		goto done;
134#endif
135#if NPIC_HEATHROW > 0
136	if (init_heathrow())
137		goto done;
138#endif
139#if NPIC_OPENPIC > 0
140	if (init_openpic(0)) {
141#ifdef MULTIPROCESSOR
142		setup_openpic_ipi();
143#endif
144		ok = 1;
145	}
146#endif
147#if NPIC_U3_HT > 0
148	if (init_u3_ht())
149		ok = 1;
150#endif
151	if (ok == 0)
152	    panic("%s: no supported interrupt controller found", __func__);
153#if NPIC_OHARE + NPIC_HEATHROW > 0
154done:
155#endif
156	oea_install_extint(pic_ext_intr);
157
158#ifdef MULTIPROCESSOR
159#if (NPIC_OHARE + NPIC_HEATHROW) > 0
160	if (OF_finddevice("/hammerhead") != -1)
161		setup_hammerhead_ipi();
162#endif
163#endif /*MULTIPROCESSOR*/
164}
165