1/* $NetBSD: bus_dma.h,v 1.14 2023/09/26 12:46:30 tsutsui Exp $ */ 2 3/* 4 * This file was extracted from alpha/include/bus.h 5 * and should probably be resynced when needed. 6 * Darrin B. Jewell <dbj@NetBSD.org> Sat Jul 31 06:11:33 UTC 1999 7 * original cvs id: NetBSD: bus.h,v 1.29 1999/06/18 04:49:24 cgd Exp 8 */ 9 10 11/*- 12 * Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc. 13 * All rights reserved. 14 * 15 * This code is derived from software contributed to The NetBSD Foundation 16 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 17 * NASA Ames Research Center. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41/* 42 * Copyright (c) 1996 Carnegie-Mellon University. 43 * All rights reserved. 44 * 45 * Author: Chris G. Demetriou 46 * 47 * Permission to use, copy, modify and distribute this software and 48 * its documentation is hereby granted, provided that both the copyright 49 * notice and this permission notice appear in all copies of the 50 * software, derivative works or modified versions, and any portions 51 * thereof, and that both notices appear in supporting documentation. 52 * 53 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 54 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 55 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 56 * 57 * Carnegie Mellon requests users of this software to return to 58 * 59 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 60 * School of Computer Science 61 * Carnegie Mellon University 62 * Pittsburgh PA 15213-3890 63 * 64 * any improvements or extensions that they make and grant Carnegie the 65 * rights to redistribute these changes. 66 */ 67 68#ifndef _M68K_BUS_DMA_H_ 69#define _M68K_BUS_DMA_H_ 70 71/* 72 * Bus DMA methods. 73 */ 74 75/* 76 * Flags used in various bus DMA methods. 77 */ 78#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 79#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 80#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 81#define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 82#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 83#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 84#define BUS_DMA_BUS2 0x020 85#define BUS_DMA_BUS3 0x040 86#define BUS_DMA_BUS4 0x080 87#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 88#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 89#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 90 91/* Forwards needed by prototypes below. */ 92struct mbuf; 93struct uio; 94 95/* 96 * Operations performed by bus_dmamap_sync(). 97 */ 98#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 99#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 100#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 101#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 102 103typedef struct m68k_bus_dma_tag *bus_dma_tag_t; 104typedef struct m68k_bus_dmamap *bus_dmamap_t; 105 106/* 107 * bus_dma_segment_t 108 * 109 * Describes a single contiguous DMA transaction. Values 110 * are suitable for programming into DMA registers. 111 */ 112struct m68k_bus_dma_segment { 113 bus_addr_t ds_addr; /* DMA address */ 114 bus_size_t ds_len; /* length of transfer */ 115 u_int _ds_flags; /* MD flags */ 116}; 117typedef struct m68k_bus_dma_segment bus_dma_segment_t; 118 119/* 120 * bus_dma_tag_t 121 * 122 * A machine-dependent opaque type describing the implementation of 123 * DMA for a given bus. 124 */ 125struct m68k_bus_dma_tag { 126 void *_cookie; /* cookie used in the guts */ 127 128 /* 129 * Some chipsets have a built-in boundary constraint, independent 130 * of what the device requests. This allows that boundary to 131 * be specified. If the device has a more restrictive constraint, 132 * the map will use that, otherwise this boundary will be used. 133 * This value is ignored if 0. 134 */ 135 bus_size_t _boundary; 136 137 /* 138 * DMA mapping methods. 139 */ 140 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 141 bus_size_t, bus_size_t, int, bus_dmamap_t *); 142 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 143 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 144 bus_size_t, struct proc *, int); 145 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 146 struct mbuf *, int); 147 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 148 struct uio *, int); 149 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 150 bus_dma_segment_t *, int, bus_size_t, int); 151 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 152 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 153 bus_addr_t, bus_size_t, int); 154 155 /* 156 * DMA memory utility functions. 157 */ 158 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 159 bus_size_t, bus_dma_segment_t *, int, int *, int); 160 void (*_dmamem_free)(bus_dma_tag_t, 161 bus_dma_segment_t *, int); 162 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 163 int, size_t, void **, int); 164 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 165 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 166 int, off_t, int, int); 167}; 168 169#define bus_dmamap_create(t, s, n, m, b, f, p) \ 170 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p)) 171#define bus_dmamap_destroy(t, p) \ 172 (*(t)->_dmamap_destroy)((t), (p)) 173#define bus_dmamap_load(t, m, b, s, p, f) \ 174 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f)) 175#define bus_dmamap_load_mbuf(t, m, b, f) \ 176 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f)) 177#define bus_dmamap_load_uio(t, m, u, f) \ 178 (*(t)->_dmamap_load_uio)((t), (m), (u), (f)) 179#define bus_dmamap_load_raw(t, m, sg, n, s, f) \ 180 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f)) 181#define bus_dmamap_unload(t, p) \ 182 (*(t)->_dmamap_unload)((t), (p)) 183#define bus_dmamap_sync(t, p, o, l, ops) \ 184 (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) 185#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \ 186 (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f)) 187#define bus_dmamem_free(t, sg, n) \ 188 (*(t)->_dmamem_free)((t), (sg), (n)) 189#define bus_dmamem_map(t, sg, n, s, k, f) \ 190 (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f)) 191#define bus_dmamem_unmap(t, k, s) \ 192 (*(t)->_dmamem_unmap)((t), (k), (s)) 193#define bus_dmamem_mmap(t, sg, n, o, p, f) \ 194 (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f)) 195 196#define bus_dmatag_subregion(t, mna, mxa, nt, f) EOPNOTSUPP 197#define bus_dmatag_destroy(t) 198 199/* 200 * bus_dmamap_t 201 * 202 * Describes a DMA mapping. 203 */ 204struct m68k_bus_dmamap { 205 /* 206 * PRIVATE MEMBERS: not for use by machine-independent code. 207 */ 208 bus_size_t _dm_size; /* largest DMA transfer mappable */ 209 int _dm_segcnt; /* number of segs this map can map */ 210 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 211 bus_size_t _dm_boundary; /* don't cross this */ 212 u_int _dm_flags; /* misc. flags */ 213 214 /* Machine dependent fields: */ 215 bus_size_t dm_xfer_len; /* length of successful transfer */ 216 217 /* 218 * PUBLIC MEMBERS: these are used by machine-independent code. 219 */ 220 bus_size_t dm_maxsegsz; /* largest possible segment */ 221 bus_size_t dm_mapsize; /* size of the mapping */ 222 int dm_nsegs; /* # valid segments in mapping */ 223 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 224 225}; 226 227#ifdef _M68K_BUS_DMA_PRIVATE 228int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 229 bus_size_t, int, bus_dmamap_t *); 230void _bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t); 231 232int _bus_dmamap_load_direct(bus_dma_tag_t, bus_dmamap_t, 233 void *, bus_size_t, struct proc *, int); 234int _bus_dmamap_load_mbuf_direct(bus_dma_tag_t, 235 bus_dmamap_t, struct mbuf *, int); 236int _bus_dmamap_load_uio_direct(bus_dma_tag_t, 237 bus_dmamap_t, struct uio *, int); 238int _bus_dmamap_load_raw_direct(bus_dma_tag_t, 239 bus_dmamap_t, bus_dma_segment_t *, int, bus_size_t, int); 240 241void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 242void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 243 bus_size_t, int); 244 245int _bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size, 246 bus_size_t alignment, bus_size_t boundary, 247 bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags); 248void _bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs, 249 int nsegs); 250int _bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs, 251 int nsegs, size_t size, void **kvap, int flags); 252void _bus_dmamem_unmap(bus_dma_tag_t tag, void *kva, 253 size_t size); 254paddr_t _bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs, 255 int nsegs, off_t off, int prot, int flags); 256#endif /* _M68K_BUS_DMA_PRIVATE */ 257 258#endif /* _M68K_BUS_DMA_H_ */ 259