1/* $NetBSD: intr.h,v 1.8 2018/11/16 19:46:52 jmcneill Exp $ */ 2 3/* XXX: cherry: To Be fixed when we switch on interrupts. */ 4 5#ifndef _IA64_INTR_H_ 6#define _IA64_INTR_H_ 7 8#include <machine/intrdefs.h> 9 10static __inline int splraise(int dummy) { return 0; } 11static __inline void spllower(int dummy) { } 12 13/* 14 * Miscellaneous 15 */ 16#define splvm() splraise(IPL_VM) 17#define splhigh() splraise(IPL_HIGH) 18#define spl0() spllower(IPL_NONE) 19#define splsched() splraise(IPL_SCHED) 20#define spllock() splhigh() 21#define splx(x) spllower(x) 22 23/* 24 * Software interrupt masks 25 */ 26 27#define splsoftclock() splraise(IPL_SOFTCLOCK) 28#define splsoftnet() splraise(IPL_SOFTNET) 29#define splsoftserial() splraise(IPL_SOFTSERIAL) 30 31typedef int ipl_t; 32typedef struct { 33 ipl_t _ipl; 34} ipl_cookie_t; 35 36static inline ipl_cookie_t 37makeiplcookie(ipl_t ipl) 38{ 39 40 return (ipl_cookie_t){._ipl = ipl}; 41} 42 43static inline int 44splraiseipl(ipl_cookie_t icookie) 45{ 46 47 return splraise(icookie._ipl); 48} 49 50 51/* 52 * Layout of the Processor Interrupt Block. 53 */ 54struct ia64_interrupt_block 55{ 56 uint64_t ib_ipi[0x20000]; /* 1Mb of IPI interrupts */ 57 uint8_t ib_reserved1[0xe0000]; 58 uint8_t ib_inta; /* Generate INTA cycle */ 59 uint8_t ib_reserved2[7]; 60 uint8_t ib_xtp; /* XTP cycle */ 61 uint8_t ib_reserved3[7]; 62 uint8_t ib_reserved4[0x1fff0]; 63}; 64 65extern uint64_t ia64_lapic_address; 66 67#define IA64_INTERRUPT_BLOCK \ 68 (struct ia64_interrupt_block *)IA64_PHYS_TO_RR6(ia64_lapic_address) 69 70/* XXX acpi */ 71typedef uint64_t intr_handle_t; 72const char *intr_string(intr_handle_t, char *, size_t); 73 74void *intr_establish(int, int, int, int (*)(void *), void *); 75void *intr_establish_xname(int, int, int, int (*)(void *), void *, const char *); 76void intr_disestablish(void *); 77void ia64_handle_intr(void *); 78 79#endif /* ! _IA64_INTR_H_ */ 80