1/* $NetBSD: via82c586reg.h,v 1.2 2000/04/22 15:00:41 uch Exp $ */ 2 3/* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Register definitions for the VIA 82c586 PCI-ISA bridge interrupt controller. 30 */ 31 32#define VP3_CFG_PIRQ_REG 0x54 /* PCI configuration space */ 33#define VP3_CFG_KBDMISCCTRL12_REG 0x44 34#define VP3_CFG_IDEMISCCTRL3_REG 0x48 35 36#define VP3_CFG_MISCCTRL2_SHIFT 24 37#define VP3_CFG_MISCCTRL2_MASK 0x0f 38#define VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE 0x20 39#define VP3_CFG_MISCCTRL2_REG(reg) \ 40 (((reg) >> VP3_CFG_MISCCTRL2_SHIFT) & VP3_CFG_MISCCTRL2_MASK) 41 42#define VP3_CFG_TRIGGER_LEVEL 0 43#define VP3_CFG_TRIGGER_EDGE 1 44 45#define VP3_CFG_TRIGGER_MASK 0x01 46#define VP3_CFG_TRIGGER_SHIFT_PIRQA 3 47#define VP3_CFG_TRIGGER_SHIFT_PIRQB 2 48#define VP3_CFG_TRIGGER_SHIFT_PIRQC 1 49#define VP3_CFG_TRIGGER_SHIFT_PIRQD 0 50 51#define VP3_CFG_INTR_MASK 0x0f 52#define VP3_PIRQ_MASK 0xdefa 53 54#define VP3_CFG_INTR_SHIFT_PIRQA 0x14 55#define VP3_CFG_INTR_SHIFT_PIRQB 0x10 56#define VP3_CFG_INTR_SHIFT_PIRQC 0x1c 57#define VP3_CFG_INTR_SHIFT_PIRQD 0x0c 58#define VP3_CFG_INTR_SHIFT_PIRQ0 0x10 59#define VP3_CFG_INTR_SHIFT_PIRQ1 0x08 60#define VP3_CFG_INTR_SHIFT_PIRQ2 0x00 61 62#define VP3_PIRQ_NONE 0 63#define VP3_LEGAL_LINK(link) ((link) >= 0 && (link) <= 6) 64#define VP3_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \ 65 ((1 << (irq)) & VP3_PIRQ_MASK) != 0) 66