1/* $NetBSD: piix.c,v 1.14 2008/04/28 20:23:25 martin Exp $ */ 2 3/*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1999, by UCHIYAMA Yasushi 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. The name of the developer may NOT be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58/* 59 * Support for the Intel PIIX PCI-ISA bridge interrupt controller 60 * and ICHn I/O controller hub 61 */ 62 63/* 64 * ICH2 and later support 8 interrupt routers while the first 65 * generation (ICH and ICH0) support 4 which is same as PIIX. 66 */ 67 68#include <sys/cdefs.h> 69__KERNEL_RCSID(0, "$NetBSD: piix.c,v 1.14 2008/04/28 20:23:25 martin Exp $"); 70 71#include <sys/param.h> 72#include <sys/systm.h> 73#include <sys/device.h> 74#include <sys/malloc.h> 75 76#include <machine/intr.h> 77#include <sys/bus.h> 78 79#include <dev/pci/pcivar.h> 80#include <dev/pci/pcireg.h> 81#include <dev/pci/pcidevs.h> 82 83#include <i386/pci/pci_intr_fixup.h> 84#include <i386/pci/piixreg.h> 85#include <i386/pci/piixvar.h> 86 87#ifdef PIIX_DEBUG 88#define DPRINTF(arg) printf arg 89#else 90#define DPRINTF(arg) 91#endif 92 93int piix_getclink(pciintr_icu_handle_t, int, int *); 94int ich_getclink(pciintr_icu_handle_t, int, int *); 95int piix_get_intr(pciintr_icu_handle_t, int, int *); 96int piix_set_intr(pciintr_icu_handle_t, int, int); 97#ifdef PIIX_DEBUG 98void piix_pir_dump(struct piix_handle *); 99void ich_pir_dump(struct piix_handle *); 100#endif 101 102const struct pciintr_icu piix_pci_icu = { 103 piix_getclink, 104 piix_get_intr, 105 piix_set_intr, 106 piix_get_trigger, 107 piix_set_trigger, 108}; 109 110const struct pciintr_icu ich_pci_icu = { 111 ich_getclink, 112 piix_get_intr, 113 piix_set_intr, 114 piix_get_trigger, 115 piix_set_trigger, 116}; 117 118static int piix_max_link = 3; 119 120int 121piix_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, 122 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 123{ 124 struct piix_handle *ph; 125 126 ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); 127 if (ph == NULL) 128 return (1); 129 130 ph->ph_iot = iot; 131 ph->ph_pc = pc; 132 ph->ph_tag = tag; 133 134 if (bus_space_map(iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 135 &ph->ph_elcr_ioh) != 0) { 136 free(ph, M_DEVBUF); 137 return (1); 138 } 139 140#ifdef PIIX_DEBUG 141 piix_pir_dump(ph); 142#endif 143 *ptagp = &piix_pci_icu; 144 *phandp = ph; 145 return (0); 146} 147 148void 149piix_uninit(pciintr_icu_handle_t v) 150{ 151 struct piix_handle *ph = v; 152 153 if (ph == NULL) 154 return; 155 156 bus_space_unmap(ph->ph_iot, ph->ph_elcr_ioh, PIIX_REG_ELCR_SIZE); 157 158 return; 159} 160 161int 162ich_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag, 163 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 164{ 165 int rv; 166 167 rv = piix_init(pc, iot, tag, ptagp, phandp); 168 169 if (rv == 0) { 170 piix_max_link = 7; 171 *ptagp = &ich_pci_icu; 172 173#ifdef PIIX_DEBUG 174 ich_pir_dump(*phandp); 175#endif 176 } 177 178 return (rv); 179} 180 181int 182piix_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 183{ 184 DPRINTF(("PIIX link value 0x%x: ", link)); 185 186 /* Pattern 1: simple. */ 187 if (PIIX_LEGAL_LINK(link - 1)) { 188 *clinkp = link - 1; 189 DPRINTF(("PIRQ %d (simple)\n", *clinkp)); 190 return (0); 191 } 192 193 /* Pattern 2: configuration register offset */ 194 if (link >= 0x60 && link <= 0x63) { 195 *clinkp = link - 0x60; 196 DPRINTF(("PIRQ %d (register offset)\n", *clinkp)); 197 return (0); 198 } 199 200 /* 201 * XXX Pattern 3: configuration register offset 1 202 * Some BIOS return 0x68, 0x69 203 */ 204 if (link >= 0x68 && link <= 0x69) { 205 *clinkp = link - 0x67; 206 DPRINTF(("PIRQ %d (register offset 1)\n", *clinkp)); 207 return (0); 208 } 209 210 DPRINTF(("bogus IRQ selection source\n")); 211 return (1); 212} 213 214int 215ich_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 216{ 217 /* 218 * configuration registers 0x68..0x6b are for PIRQ[EFGH] 219 */ 220 if (link >= 0x68 && link <= 0x6b) { 221 *clinkp = link - 0x68 + 4; 222 DPRINTF(("PIIX link value 0x%x: ", link)); 223 DPRINTF(("PIRQ %d (register offset)\n", *clinkp)); 224 return (0); 225 } 226 227 return piix_getclink(v, link, clinkp); 228} 229 230int 231piix_get_intr(pciintr_icu_handle_t v, int clink, int *irqp) 232{ 233 struct piix_handle *ph = v; 234 int shift; 235 pcireg_t reg; 236 int cfgreg; 237 238 if (PIIX_LEGAL_LINK(clink) == 0) 239 return (1); 240 241 cfgreg = clink <= 3 ? PIIX_CFG_PIRQ : PIIX_CFG_PIRQ2; 242 clink &= 0x03; 243 244 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg); 245 shift = clink << 3; 246 if ((reg >> shift) & PIIX_CFG_PIRQ_NONE) 247 *irqp = X86_PCI_INTERRUPT_LINE_NO_CONNECTION; 248 else 249 *irqp = PIIX_PIRQ(reg, clink); 250 251 return (0); 252} 253 254int 255piix_set_intr(pciintr_icu_handle_t v, int clink, int irq) 256{ 257 struct piix_handle *ph = v; 258 int shift; 259 pcireg_t reg; 260 int cfgreg; 261 262 if (PIIX_LEGAL_LINK(clink) == 0 || PIIX_LEGAL_IRQ(irq) == 0) 263 return (1); 264 265 cfgreg = clink <= 3 ? PIIX_CFG_PIRQ : PIIX_CFG_PIRQ2; 266 clink &= 0x03; 267 268 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg); 269 shift = clink << 3; 270 reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift); 271 reg |= irq << shift; 272 pci_conf_write(ph->ph_pc, ph->ph_tag, cfgreg, reg); 273 274 return (0); 275} 276 277int 278piix_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp) 279{ 280 struct piix_handle *ph = v; 281 int off, bit; 282 uint8_t elcr; 283 284 if (PIIX_LEGAL_IRQ(irq) == 0) 285 return (1); 286 287 off = (irq > 7) ? 1 : 0; 288 bit = irq & 7; 289 290 elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); 291 if (elcr & (1 << bit)) 292 *triggerp = IST_LEVEL; 293 else 294 *triggerp = IST_EDGE; 295 296 return (0); 297} 298 299int 300piix_set_trigger(pciintr_icu_handle_t v, int irq, int trigger) 301{ 302 struct piix_handle *ph = v; 303 int off, bit; 304 uint8_t elcr; 305 306 if (PIIX_LEGAL_IRQ(irq) == 0) 307 return (1); 308 309 off = (irq > 7) ? 1 : 0; 310 bit = irq & 7; 311 312 elcr = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, off); 313 if (trigger == IST_LEVEL) 314 elcr |= (1 << bit); 315 else 316 elcr &= ~(1 << bit); 317 bus_space_write_1(ph->ph_iot, ph->ph_elcr_ioh, off, elcr); 318 319 return (0); 320} 321 322#ifdef PIIX_DEBUG 323void 324piix_pir_dump(struct piix_handle *ph) 325{ 326 int i, irq; 327 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ); 328 uint8_t elcr[2]; 329 330 elcr[0] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 0); 331 elcr[1] = bus_space_read_1(ph->ph_iot, ph->ph_elcr_ioh, 1); 332 333 for (i = 0; i < 4; i++) { 334 irq = PIIX_PIRQ(irqs, i); 335 if (irq & PIIX_CFG_PIRQ_NONE) 336 printf("PIIX PIRQ %d: irq none (0x%x)\n", i, irq); 337 else 338 printf("PIIX PIRQ %d: irq %d\n", i, irq); 339 } 340 printf("PIIX irq:"); 341 for (i = 0; i < 16; i++) 342 printf(" %2d", i); 343 printf("\n"); 344 printf(" trigger:"); 345 for (i = 0; i < 16; i++) 346 printf(" %c", (elcr[(i & 8) ? 1 : 0] & (1 << (i & 7))) ? 347 'L' : 'E'); 348 printf("\n"); 349} 350 351void 352ich_pir_dump(struct piix_handle *ph) 353{ 354 int i, irq; 355 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ2); 356 357 for (i = 0; i < 4; i++) { 358 irq = PIIX_PIRQ(irqs, i); 359 if (irq & PIIX_CFG_PIRQ_NONE) 360 printf("PIIX PIRQ %d: irq none (0x%x)\n", i+4, irq); 361 else 362 printf("PIIX PIRQ %d: irq %d\n", i+4, irq); 363 } 364} 365#endif /* PIIX_DEBUG */ 366