1/*	$NetBSD: amd756reg.h,v 1.1 2001/04/19 17:32:40 uch Exp $	*/
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * Register definitions for the AMD756 Peripheral Bus Controller.
31 */
32
33/*
34 * Edge Triggered Interrupt Select register. (0x54)
35 * bits 7-4: reserved
36 * bit 3: Edge Triggered Interrupt Select for PCI Interrupt D
37 * bit 2: Edge Triggered Interrupt Select for PCI Interrupt C
38 * bit 1: Edge Triggered Interrupt Select for PCI Interrupt B
39 * bit 0: Edge Triggered Interrupt Select for PCI Interrupt A
40 *   0 = active Low and level triggered
41 *   1 = active High and edge triggered
42 *
43 * PIRQ Select register. (0x56-57)
44 * bits 15-12: PIRQD# Select
45 * bits 11-8:  PIRQD# Select
46 * bits 7-4:   PIRQD# Select
47 * bits 3-0:   PIRQD# Select
48 *   0000: Reserved  0100: IRQ4      1000: Reserved  1100: IRQ12
49 *   0001: IRQ1      0101: IRQ5      1001: IRQ9      1101: Reserved
50 *   0010: Reserved  0110: IRQ6      1010: IRQ10     1110: IRQ14
51 *   0011: IRQ3      0111: IRQ7      1011: IRQ11     1111: IRQ15
52 */
53#define AMD756_CFG_PIR			0x54
54
55#define AMD756_GET_EDGESEL(ph)						  \
56		(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \
57		 & 0xff)
58
59#define AMD756_GET_PIIRQSEL(ph)						  \
60		(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \
61		 >> 16)
62
63#define AMD756_SET_EDGESEL(ph, n)					  \
64		pci_conf_write((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR, \
65		(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \
66		 & 0xffff0000) | (n))
67
68#define AMD756_SET_PIIRQSEL(ph, n)					  \
69		pci_conf_write((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR, \
70		(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \
71		 & 0x000000ff) | ((n) << 16))
72
73#define AMD756_PIRQ_MASK	0xdefa
74#define	AMD756_LEGAL_LINK(link)	((link) >= 0 && (link) <= 3)
75#define AMD756_LEGAL_IRQ(irq)	((irq) >= 0 && (irq) <= 15 && 		 \
76				 ((1 << (irq)) & AMD756_PIRQ_MASK) != 0)
77