1/*	$NetBSD: hd64465intcreg.h,v 1.1 2002/02/11 17:27:15 uch Exp $	*/
2
3/*-
4 * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/* Interrupt Request Register (16bit) */
33#define HD64465_NIRR					0xb0005000
34/* Interrupt Mask Register (16bit) */
35#define HD64465_NIMR					0xb0005002
36/* Interrupt Trigger Mode Register (16bit) */
37#define HD64465_NITR					0xb0005004
38
39/* common defines. */
40#define   HD64465_PS2KB		0x8000
41#define   HD64465_PCC0		0x4000
42#define   HD64465_PCC1		0x2000
43#define   HD64465_AFE		0x1000
44#define   HD64465_GPIO		0x0800
45#define   HD64465_TMU0		0x0400
46#define   HD64465_TMU1		0x0200
47#define   HD64465_KBC		0x0100
48#define   HD64465_PS2MS		0x0080
49#define   HD64465_IRDA		0x0040
50#define   HD64465_UART		0x0020
51#define   HD64465_PPR		0x0008
52#define   HD64465_SCDI		0x0004
53#define   HD64465_OHCI		0x0002
54#define   HD64465_ADC		0x0001
55