1/*- 2 * Copyright (c) 2001 SATO Kazumi, All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29/* 30 * definition for identify VR series cpu 31 * $NetBSD: vrcpudef.h,v 1.3 2001/09/07 16:02:56 sato Exp $ 32 * 33 * REQUIRE #include "opt_vr41xx.h" before using this header. 34 */ 35#include "opt_vr41xx.h" 36 37/* 38 * VR cpu id 39 * It is related with BCU cpu id. 40 * KEEP consistency with bcureg.h 41 */ 42#define VRID_4101 0x0 /* VR4101 */ 43#define VRID_4102 0x1 /* VR4102 */ 44#define VRID_4111 0x2 /* VR4111 */ 45#define VRID_4121 0x3 /* VR4121 */ 46#define VRID_4122 0x4 /* VR4122 */ 47#define VRID_4131 0x5 /* VR4131 */ 48/* conflict other cpu */ 49#define VRID_4181 0x10 /* VR4181 conflict VR4101 */ 50 51/* 52 * VR cpu architecure group 53 * 54 * vr41xx group: all vr cpus (some registers are same) 55 * vr4181 group: vr4181 (vrip address and registers are same) 56 * vr4101 group: vr4101??? 57 * vr4102 group: vr4102, vr4111, vr4121, vr4122 (some resgiters are same) 58 * or vr4102, vr4111, vr4121 (vrip address and registers are same) 59 * vr4111 group: vr4111, vr4121, vr4122 (some registers are same) 60 * or vr4111, vr4121 (vrip address and registers are same) 61 * vr4122 group: vr4122, vr4131 (vrip address and registers are same) 62 * 63 * REQUIRE #include "opt_vr41xx.h" before using this definition. 64 */ 65#if defined VR4181 66#define VRGROUP_4181 VRID_4181 67#endif /* defined VR4181 */ 68 69#if defined VR4101 70#define VRGROUP_4101 VRID_4101 71#endif /* defined VR4101 */ 72 73#if defined VR4102 74#define VRGROUP_4102 VRID_4102 75#define VRGROUP_4102_4121 VRID_4102 76#define VRGROUP_4102_4122 VRID_4102 77#define VRGROUP_4102_4131 VRID_4102 78#endif /* defined VR4102 */ 79 80#if defined VR4111 81#define VRGROUP_4111_4121 VRID_4111 82#define VRGROUP_4111_4122 VRID_4111 83#define VRGROUP_4111_4131 VRID_4111 84 85#ifndef VRGROUP_4102_4121 86#define VRGROUP_4102_4121 VRID_4111 87#endif /* VRGROUP_4102_4121 */ 88 89#ifndef VRGROUP_4102_4122 90#define VRGROUP_4102_4122 VRID_4111 91#endif /* VRGROUP_4102_4122 */ 92 93#ifndef VRGROUP_4102_4131 94#define VRGROUP_4102_4131 VRID_4111 95#endif /* VRGROUP_4102_4131 */ 96 97#endif /* defined VR4111 */ 98 99#if defined VR4121 100#define VRGROUP_4121_4122 VRID_4121 101#define VRGROUP_4121_4131 VRID_4131 102 103#ifndef VRGROUP_4111_4121 104#define VRGROUP_4111_4121 VRID_4121 105#endif /* VRGROUP_4111_4121 */ 106 107#ifndef VRGROUP_4111_4122 108#define VRGROUP_4111_4122 VRID_4121 109#endif /* VRGROUP_4111_4122 */ 110 111#ifndef VRGROUP_4111_4131 112#define VRGROUP_4111_4131 VRID_4121 113#endif /* VRGROUP_4111_4131 */ 114 115#ifndef VRGROUP_4102_4121 116#define VRGROUP_4102_4121 VRID_4121 117#endif /* VRGROUP_4102_4121 */ 118 119#ifndef VRGROUP_4102_4122 120#define VRGROUP_4102_4122 VRID_4121 121#endif /* VRGROUP_4102_4122 */ 122 123#ifndef VRGROUP_4102_4131 124#define VRGROUP_4102_4131 VRID_4121 125#endif /* VRGROUP_4102_4131 */ 126 127#endif /* VR4121 */ 128 129 130#if defined VR4122 131#define VRGROUP_4122 VRID_4122 132 133#ifndef VRGROUP_4122_4131 134#define VRGROUP_4122_4131 VRID_4122 135#endif /* VRGROUP_4122_4131 */ 136 137#ifndef VRGROUP_4111_4122 138#define VRGROUP_4111_4122 VRID_4122 139#endif /* VRGROUP_4111_4122 */ 140 141#ifndef VRGROUP_4111_4131 142#define VRGROUP_4111_4131 VRID_4122 143#endif /* VRGROUP_4111_4131 */ 144 145#ifndef VRGROUP_4102_4122 146#define VRGROUP_4102_4122 VRID_4122 147#endif /* VRGROUP_4102_4122 */ 148 149#ifndef VRGROUP_4102_4131 150#define VRGROUP_4102_4131 VRID_4122 151#endif /* VRGROUP_4102_4131 */ 152 153#endif /* VR4122 */ 154 155#if defined VR4131 156#define VRGROUP_4131 VRID_4131 157 158#ifndef VRGROUP_4122_4131 159#define VRGROUP_4122_4131 VRID_4131 160#endif /* VRGROUP_4122_4131 */ 161 162#ifndef VRGROUP_4111_4131 163#define VRGROUP_4111_4131 VRID_4131 164#endif /* VRGROUP_4111_4131 */ 165 166#ifndef VRGROUP_4102_4131 167#define VRGROUP_4102_4131 VRID_4131 168#endif /* VRGROUP_4102_4131 */ 169 170#endif /* VR4131 */ 171 172/* 173 * identify one cpu only 174 */ 175#if defined VR4181 && !defined VR4101 && !defined VRGROUP_4102_4131 176#define ONLY_VR4181 VRID_4181 177#endif /* ONLY_VR4181 */ 178 179#if !defined VR4181 && defined VR4101 && !defined VRGROUP_4102_4131 180#define ONLY_VR4101 VRID_4101 181#endif /* ONLY_VR4101 */ 182 183#if !defined VRGROUP_4181 && !defined VRGROUP_4101 && defined VR4102 && !defined VRGROUP_4111_4131 184#define ONLY_VR4102 VRID_4102 185#endif /* ONLY_VR4102 */ 186 187#if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VR4102 && defined VRGROUP_4111_4121 && !defined VRGROUP_4122_4131 188#define ONLY_VR4111_4121 VRGROUP_4111_4121 189#endif /* ONLY_VR4111_4121 */ 190 191#if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VRGROUP_4102_4121 && defined VR4122 && !defined VRGROUP_4131 192#define ONLY_VR4122 VRID4122 193#endif /* ONLY_VR4122 */ 194 195#if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VRGROUP_4102_4121 && !defined VRGROUP_4122 && defined VR4131 196#define ONLY_VR4131 VRID4131 197#endif /* ONLY_VR4131 */ 198 199#if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VRGROUP_4102_4121 && defined VRGROUP_4122_4131 200#define ONLY_VR4122_4131 VRGROUP_4122_4131 201#endif /* ONLY_VR4131 */ 202 203 204 205#if defined ONLY_VR4181 206#define ONLY_VR_SPECIFIED ONLY_VR4181 207#endif /* defined ONLY_VR4181 */ 208 209#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4101 210#define ONLY_VR_SPECIFIED ONLY_VR4101 211#endif /* defined ONLY_VR4101 */ 212 213#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4102 214#define ONLY_VR_SPECIFIED ONLY_VR4102 215#endif /* defined ONLY_VR4102 */ 216 217#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4111_4121 218#define ONLY_VR_SPECIFIED ONLY_VR4111_4121 219#endif /* defined ONLY_VR4111_4121 */ 220 221#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4122_4131 222#define ONLY_VR_SPECIFIED ONLY_VR4122_4131 223#endif /* ONLY_VR4122 */ 224 225#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4122 226#define ONLY_VR_SPECIFIED ONLY_VR4122 227#endif /* ONLY_VR4122 */ 228 229#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4131 230#define ONLY_VR_SPECIFIED ONLY_VR4131 231#endif /* ONLY_VR4131 */ 232 233/* 234 * identify single vrip base address 235 */ 236#if defined ONLY_VR4181 237#define SINGLE_VRIP_BASE ONLY_VR4181 238#endif /* defined ONLY_VR4181 */ 239 240#if !defined VR4181 && defined VRGROUP_4102_4121 && !defined VRGROUP_4122_4131 241#define SINGLE_VRIP_BASE VRGROUP_4102_4121 242#endif 243 244#if !defined VR4181 && !defined VRGROUP_4102_4121 && defined VRGROUP_4122_4131 245#define SINGLE_VRIP_BASE VRGROUP_4122_4131 246#endif 247 248/* end */ 249