machdep.c revision 1.7
1/* $NetBSD: machdep.c,v 1.7 2016/08/26 13:51:55 skrll Exp $ */ 2 3/* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department, The Mach Operating System project at 45 * Carnegie-Mellon University and Ralph Campbell. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 * from: Utah Hdr: machdep.c 1.63 91/04/24 73 */ 74/* 75 * Copyright (c) 1988 University of Utah. 76 * 77 * This code is derived from software contributed to Berkeley by 78 * the Systems Programming Group of the University of Utah Computer 79 * Science Department, The Mach Operating System project at 80 * Carnegie-Mellon University and Ralph Campbell. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 2. Redistributions in binary form must reproduce the above copyright 88 * notice, this list of conditions and the following disclaimer in the 89 * documentation and/or other materials provided with the distribution. 90 * 3. All advertising materials mentioning features or use of this software 91 * must display the following acknowledgement: 92 * This product includes software developed by the University of 93 * California, Berkeley and its contributors. 94 * 4. Neither the name of the University nor the names of its contributors 95 * may be used to endorse or promote products derived from this software 96 * without specific prior written permission. 97 * 98 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 99 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 100 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 101 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 102 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 103 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 108 * SUCH DAMAGE. 109 * 110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 111 * from: Utah Hdr: machdep.c 1.63 91/04/24 112 */ 113 114#include "opt_multiprocessor.h" 115 116#include <sys/cdefs.h> 117__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.7 2016/08/26 13:51:55 skrll Exp $"); 118 119#include <sys/param.h> 120#include <sys/systm.h> 121#include <sys/kernel.h> 122#include <sys/buf.h> 123#include <sys/cpu.h> 124#include <sys/reboot.h> 125#include <sys/mount.h> 126#include <sys/kcore.h> 127#include <sys/boot_flag.h> 128#include <sys/termios.h> 129#include <sys/ksyms.h> 130 131#include <uvm/uvm_extern.h> 132 133#include <dev/cons.h> 134 135#include "ksyms.h" 136 137#if NKSYMS || defined(DDB) || defined(LKM) 138#include <machine/db_machdep.h> 139#include <ddb/db_extern.h> 140#endif 141 142#include <machine/psl.h> 143#include <machine/locore.h> 144 145#include <mips/cavium/autoconf.h> 146#include <mips/cavium/octeonvar.h> 147#include <mips/cavium/include/iobusvar.h> 148#include <mips/cavium/include/bootbusvar.h> 149 150#include <mips/cavium/dev/octeon_uartreg.h> 151#include <mips/cavium/dev/octeon_ciureg.h> 152#include <mips/cavium/dev/octeon_gpioreg.h> 153 154#include <evbmips/cavium/octeon_uboot.h> 155 156static void mach_init_bss(void); 157static void mach_init_vector(void); 158static void mach_init_bus_space(void); 159static void mach_init_console(void); 160static void mach_init_memory(u_quad_t); 161 162#include "com.h" 163#if NCOM > 0 164#include <dev/ic/comreg.h> 165#include <dev/ic/comvar.h> 166int comcnrate = 115200; /* XXX should be config option */ 167#endif /* NCOM > 0 */ 168 169/* Maps for VM objects. */ 170struct vm_map *phys_map = NULL; 171 172int netboot; 173 174phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 175int mem_cluster_cnt; 176 177void mach_init(uint64_t, uint64_t, uint64_t, uint64_t); 178 179struct octeon_config octeon_configuration; 180struct octeon_btinfo octeon_btinfo; 181 182char octeon_nmi_stack[PAGE_SIZE] __section(".data1") __aligned(PAGE_SIZE); 183 184/* 185 * Do all the stuff that locore normally does before calling main(). 186 */ 187void 188mach_init(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3) 189{ 190 uint64_t btinfo_paddr; 191 u_quad_t memsize; 192 int corefreq; 193 194 mach_init_bss(); 195 196 KASSERT(MIPS_XKPHYS_P(arg3)); 197 btinfo_paddr = mips3_ld(arg3 + OCTEON_BTINFO_PADDR_OFFSET); 198 199 /* Should be in first 256MB segment */ 200 KASSERT(btinfo_paddr < 256 * 1024 * 1024); 201 memcpy(&octeon_btinfo, 202 (struct octeon_btinfo *)MIPS_PHYS_TO_KSEG0(btinfo_paddr), 203 sizeof(octeon_btinfo)); 204 205 corefreq = octeon_btinfo.obt_eclock_hz; 206 memsize = octeon_btinfo.obt_dram_size * 1024 * 1024; 207 208 octeon_cal_timer(corefreq); 209 210 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 211 case 0: cpu_setmodel("Cavium Octeon CN38XX/CN36XX"); break; 212 case 1: cpu_setmodel("Cavium Octeon CN31XX/CN3020"); break; 213 case 2: cpu_setmodel("Cavium Octeon CN3005/CN3010"); break; 214 case 3: cpu_setmodel("Cavium Octeon CN58XX"); break; 215 case 4: cpu_setmodel("Cavium Octeon CN5[4-7]XX"); break; 216 case 6: cpu_setmodel("Cavium Octeon CN50XX"); break; 217 case 7: cpu_setmodel("Cavium Octeon CN52XX"); break; 218 default: cpu_setmodel("Cavium Octeon"); break; 219 } 220 221 mach_init_vector(); 222 223 /* set the VM page size */ 224 uvm_setpagesize(); 225 226 mach_init_bus_space(); 227 228 mach_init_console(); 229 230 mach_init_memory(memsize); 231 232 /* 233 * Allocate uarea page for lwp0 and set it. 234 */ 235 mips_init_lwp0_uarea(); 236 237 boothowto = RB_AUTOBOOT; 238 boothowto |= AB_VERBOSE; 239 240#if 0 241 curcpu()->ci_nmi_stack = octeon_nmi_stack + sizeof(octeon_nmi_stack) - sizeof(struct kernframe); 242 *(uint64_t *)MIPS_PHYS_TO_KSEG0(0x800) = (intptr_t)octeon_reset_vector; 243 const uint64_t wdog_reg = MIPS_PHYS_TO_XKPHYS_UNCACHED(CIU_WDOG0); 244 uint64_t wdog = mips3_ld(wdog_reg); 245 wdog &= ~(CIU_WDOGX_MODE|CIU_WDOGX_LEN); 246 wdog |= __SHIFTIN(3, CIU_WDOGX_MODE); 247 wdog |= CIU_WDOGX_LEN; // max period 248 mips64_sd_a64(wdog_reg, wdog); 249 printf("Watchdog enabled!\n"); 250#endif 251 252#if defined(DDB) 253 if (boothowto & RB_KDB) 254 Debugger(); 255#endif 256} 257 258void 259consinit(void) 260{ 261 262 /* 263 * Everything related to console initialization is done 264 * in mach_init(). 265 */ 266} 267 268void 269mach_init_bss(void) 270{ 271 extern char edata[], end[]; 272 273 /* 274 * Clear the BSS segment. 275 */ 276 memset(edata, 0, mips_round_page(end) - (uintptr_t)edata); 277} 278 279void 280mach_init_vector(void) 281{ 282 283 /* Make sure exception base at 0 (MIPS_COP_0_EBASE) */ 284 __asm __volatile("mtc0 %0, $15, 1" : : "r"(0x80000000) ); 285 286 /* 287 * Set up the exception vectors and CPU-specific function 288 * vectors early on. We need the wbflush() vector set up 289 * before comcnattach() is called (or at least before the 290 * first printf() after that is called). 291 * Also clears the I+D caches. 292 */ 293 mips_vector_init(NULL, true); 294} 295 296void 297mach_init_bus_space(void) 298{ 299 struct octeon_config *mcp = &octeon_configuration; 300 301 octeon_dma_init(mcp); 302 303 iobus_bootstrap(mcp); 304 bootbus_bootstrap(mcp); 305} 306 307void 308mach_init_console(void) 309{ 310#if NCOM > 0 311 struct octeon_config *mcp = &octeon_configuration; 312 int status; 313 extern int octeon_uart_com_cnattach(bus_space_tag_t, int, int); 314 315 /* 316 * Delay to allow firmware putchars to complete. 317 * FIFO depth * character time. 318 * character time = (1000000 / (defaultrate / 10)) 319 */ 320 delay(640000000 / comcnrate); 321 322 status = octeon_uart_com_cnattach( 323 &mcp->mc_iobus_bust, 324 0, /* XXX port 0 */ 325 comcnrate); 326 if (status != 0) 327 panic("can't initialize console!"); /* XXX print to nowhere! */ 328#else 329 panic("octeon: not configured to use serial console"); 330#endif /* NCOM > 0 */ 331} 332 333void 334mach_init_memory(u_quad_t memsize) 335{ 336 extern char kernel_text[]; 337 extern char end[]; 338 339 physmem = btoc(memsize); 340 341 if (memsize <= 256 * 1024 * 1024) { 342 mem_clusters[0].start = 0; 343 mem_clusters[0].size = memsize; 344 mem_cluster_cnt = 1; 345 } else if (memsize <= 512 * 1024 * 1024) { 346 mem_clusters[0].start = 0; 347 mem_clusters[0].size = 256 * 1024 * 1024; 348 mem_clusters[1].start = 0x410000000ULL; 349 mem_clusters[1].size = memsize - 256 * 1024 * 1024; 350 mem_cluster_cnt = 2; 351 } else { 352 mem_clusters[0].start = 0; 353 mem_clusters[0].size = 256 * 1024 * 1024; 354 mem_clusters[1].start = 0x20000000; 355 mem_clusters[1].size = memsize - 512 * 1024 * 1024; 356 mem_clusters[2].start = 0x410000000ULL; 357 mem_clusters[2].size = 256 * 1024 * 1024; 358 mem_cluster_cnt = 3; 359 } 360 361 362#ifdef MULTIPROCESSOR 363 const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM; 364 mem_clusters[0].start = cores * 4096; 365#endif 366 367 /* 368 * Load the rest of the available pages into the VM system. 369 */ 370 mips_page_physload(mips_trunc_page(kernel_text), mips_round_page(end), 371 mem_clusters, mem_cluster_cnt, NULL, 0); 372 373 /* 374 * Initialize error message buffer (at end of core). 375 */ 376 mips_init_msgbuf(); 377 378 pmap_bootstrap(); 379} 380 381/* 382 * cpu_startup 383 * cpu_reboot 384 */ 385 386int waittime = -1; 387 388/* 389 * Allocate memory for variable-sized tables, 390 */ 391void 392cpu_startup(void) 393{ 394#ifdef MULTIPROCESSOR 395 // Create a kcpuset so we can see on which CPUs the kernel was started. 396 kcpuset_create(&cpus_booted, true); 397#endif 398 399 /* 400 * Do the common startup items. 401 */ 402 cpu_startup_common(); 403 404 /* 405 * Virtual memory is bootstrapped -- notify the bus spaces 406 * that memory allocation is now safe. 407 */ 408 octeon_configuration.mc_mallocsafe = 1; 409} 410 411void 412cpu_reboot(int howto, char *bootstr) 413{ 414 415 /* Take a snapshot before clobbering any registers. */ 416 savectx(curpcb); 417 418 if (cold) { 419 howto |= RB_HALT; 420 goto haltsys; 421 } 422 423 /* If "always halt" was specified as a boot flag, obey. */ 424 if (boothowto & RB_HALT) 425 howto |= RB_HALT; 426 427 boothowto = howto; 428 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 429 waittime = 0; 430 vfs_shutdown(); 431 432 /* 433 * If we've been adjusting the clock, the todr 434 * will be out of synch; adjust it now. 435 */ 436 resettodr(); 437 } 438 439 splhigh(); 440 441 if (howto & RB_DUMP) 442 dumpsys(); 443 444haltsys: 445 doshutdownhooks(); 446 447 if (howto & RB_HALT) { 448 printf("\n"); 449 printf("The operating system has halted.\n"); 450 printf("Please press any key to reboot.\n\n"); 451 } 452 453 printf("%s\n\n", ((howto & RB_HALT) != 0) ? "halted." : "rebooting..."); 454 455 /* 456 * Need a small delay here, otherwise we see the first few characters of 457 * the warning below. 458 */ 459 delay(80000); 460 461 /* initiate chip soft-reset */ 462 uint64_t fuse = octeon_read_csr(CIU_FUSE); 463 octeon_write_csr(CIU_SOFT_BIST, fuse); 464 octeon_read_csr(CIU_SOFT_RST); 465 octeon_write_csr(CIU_SOFT_RST, fuse); 466 467 delay(1000000); 468 469 printf("WARNING: reset failed!\nSpinning..."); 470 471 for (;;) 472 /* spin forever */ ; /* XXX */ 473} 474