1/*	$NetBSD: mach_intr.c,v 1.4 2023/12/20 14:12:25 thorpej Exp $	*/
2
3/*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Platform-specific interrupt support for the Alchemy parts.
34 *
35 * These boards just use the interrupt controller built into the
36 * Alchemy processors, so we just provide evbmips-compliant wrapper
37 * routines.
38 */
39
40#include <sys/cdefs.h>
41__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.4 2023/12/20 14:12:25 thorpej Exp $");
42
43#include "opt_ddb.h"
44
45#include <sys/param.h>
46#include <sys/bus.h>
47#include <sys/lwp.h>
48#include <sys/device.h>
49#include <sys/intr.h>
50#include <sys/kernel.h>
51#include <sys/systm.h>
52
53#include <mips/locore.h>
54#include <mips/cavium/octeonvar.h>
55
56void
57evbmips_intr_init(void)
58{
59	octeon_intr_init(curcpu());
60}
61
62void
63evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
64{
65
66	octeon_iointr(ipl, cf->pc, ipending);
67}
68