1/* $NetBSD: smdk2800_start.S,v 1.7 2005/12/11 12:17:09 christos Exp $ */ 2 3/* 4 * Copyright (c) 2002, 2005 Fujitsu Component Limited 5 * Copyright (c) 2002, 2005 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35#include <machine/asm.h> 36#include <arm/armreg.h> 37#include "assym.h" 38 39#include <arm/s3c2xx0/s3c2800reg.h> /* for S3C2800_DBANK0_START */ 40 41#include <evbarm/smdk2xx0/smdk2800var.h> 42 43RCSID("$NetBSD$") 44 45/* 46 * Kernel start routine for Samsung SMDK2800. 47 * This code is excuted at the very first after the kernel is loaded 48 * by boot program on ROM or gzboot. 49 */ 50 .text 51 52#define KERNEL_TEXT_ADDR (SDRAM_START+0x00200000) 53 54 .global _C_LABEL(smdk2800_start) 55_C_LABEL(smdk2800_start): 56 /* Are we running on right place ? */ 57 adr r0, _C_LABEL(smdk2800_start) 58 cmp r0, #KERNEL_TEXT_ADDR 59 beq smdk2800_start_ram 60 61 /* move me to RAM 62 * XXX: we can use memcpy if it is PIC 63 */ 64 ldr r1, Lcopy_size 65 adr r0, _C_LABEL(smdk2800_start) 66 add r1, r1, #3 67 mov r1, r1, LSR #2 68 mov r2, #KERNEL_TEXT_ADDR 69 mov r4, r2 70 71 cmp r0, r2 72 bhs 5f 73 74 /* src < dest. copy from top */ 75 add r0,r0,r1,LSL #2 76 add r2,r2,r1,LSL #2 77 783: ldr r3,[r0,#-4]! 79 str r3,[r2,#-4]! 80 subs r1,r1,#1 81 bhi 3b 82 b 7f 83 84 /* src >= dest. copy from bottom */ 855: ldr r3,[r0],#4 86 str r3,[r2],#4 87 subs r1,r1,#1 88 bhi 5b 89 907: 91 /* Jump to RAM */ 92 ldr r0, Lstart_off 93 add pc, r4, r0 94 95Lcopy_size: .word _edata-_C_LABEL(smdk2800_start) 96Lstart_off: .word smdk2800_start_ram-_C_LABEL(smdk2800_start) 97 98smdk2800_start_ram: 99 /* 100 * Kernel is loaded in SDRAM (0x08200000..), and is expected to run 101 * in VA 0xc0200000.. 102 */ 103 104 /* Disable MMU for a while */ 105 mrc p15, 0, r2, c1, c0, 0 106 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 107 mcr p15, 0, r2, c1, c0, 0 108 109 nop 110 nop 111 nop 112 113 mov r0,#SDRAM_START /* pagetable */ 114 adr r4, mmu_init_table 115 b 2f 1161: 117 str r3, [r0, r2] 118 add r2, r2, #4 119 add r3, r3, #(L1_S_SIZE) 120 adds r1, r1, #-1 121 bhi 1b 1222: 123 ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */ 124 cmp r1, #0 125 bne 1b 126 127 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 128 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 129 130 /* Set the Domain Access register. Very important! */ 131 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 132 mcr p15, 0, r0, c3, c0, 0 133 134 /* Enable MMU */ 135 mrc p15, 0, r0, c1, c0, 0 136 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 137 mcr p15, 0, r0, c1, c0, 0 138 139 nop 140 nop 141 nop 142 143 /* Jump to kernel code in TRUE VA */ 144 adr r0, Lstart 145 ldr pc, [r0] 146 147Lstart: 148 .word start 149 150#define MMU_INIT(va,pa,n_sec,attr) \ 151 .word n_sec ; \ 152 .word 4*((va)>>L1_S_SHIFT) ; \ 153 .word (pa)|(attr) ; 154 155mmu_init_table: 156 /* fill all table VA==PA */ 157 MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP_KRW) 158 /* map SDRAM VA==PA, WT cacheable */ 159 MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP_KRW) 160 /* map VA 0xc0000000..0xc3ffffff to PA 0x08000000..0x0bffffff */ 161 MMU_INIT(0xc0000000, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP_KRW) 162 163 /* Map all built-in peripheral registers at 0xfd000000 */ 164 MMU_INIT(SMDK2800_IO_AREA_VBASE, S3C2800_PERIPHERALS, 2, L1_TYPE_S|L1_S_AP_KRW) 165 .word 0 /* end of table */ 166 167