1/* $NetBSD: gtreg.h,v 1.3 2006/04/09 01:24:05 tsutsui Exp $ */ 2/* 3 * Copyright (c) 2003 4 * KIYOHARA Takashi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#define GT_TIMER_COUNTER0 0x850 28#define GT_TIMER_COUNTER1 0x854 29#define GT_TIMER_COUNTER2 0x858 30#define GT_TIMER_COUNTER3 0x85c 31 32#define GT_TIMER_CTRL 0x864 33#define ENTC0 0x01 34#define TCSEL0 0x02 35#define ENTC1 0x04 36#define TCSEL1 0x08 37#define ENTC2 0x10 38#define TCSEL2 0x20 39#define ENTC3 0x40 40#define TCSEL3 0x80 41 42#define GT_PCI_COMMAND 0xc00 43#define PCI_BYTESWAP 0x00000001 44#define PCI_SYNCMODE 0x00000006 45#define PCI_PCLK_LOW 0x00000000 46#define PCI_PCLK_HIGH 0x00000002 47#define PCI_PCLK_SYNC 0x00000004 48 49#define GT_PCI_TIMEOUT_RETRY 0xc04 50#define PCI_TIMEOUT0 0x000000ff 51#define PCI_TIMEOUT1 0x0000ff00 52#define PCI_TIMEOUT1_SHIFT 8 53#define PCI_RETRYCTR 0x00ff0000 54#define PCI_RETRYCTR_SHIFT 16 55 56#define GT_INTR_CAUSE 0xc18 57#define INTSUM 0x00000001 58#define MEMOUT 0x00000002 59#define DMAOUT 0x00000004 60#define MASTEROUT 0x00000008 61#define DMA0COMP 0x00000010 62#define DMA1COMP 0x00000020 63#define DMA2COMP 0x00000040 64#define DMA3COMP 0x00000080 65#define T0EXP 0x00000100 66#define T1EXP 0x00000200 67#define T2EXP 0x00000400 68#define T3EXP 0x00000800 69#define MASRDERR 0x00001000 70#define SLVWRERR 0x00002000 71#define MASWRERR 0x00004000 72#define SLVRDERR 0x00008000 73#define ADDRERR 0x00010000 74#define MEMERR 0x00020000 75#define MASABORT 0x00040000 76#define TARABORT 0x00080000 77#define RETRYCTR 0x00100000 78#define MASTER_INT0 0x00200000 79#define MASTER_INT1 0x00400000 80#define MASTER_INT2 0x00800000 81#define MASTER_INT3 0x01000000 82#define MASTER_INT4 0x02000000 83#define PCI_INT0 0x04000000 84#define PCI_INT1 0x08000000 85#define PCI_INT2 0x10000000 86#define PCI_INT3 0x20000000 87#define MASTER_INTSUM 0x40000000 88#define PCI_INTSUM 0x80000000 89 90#define GT_MASTER_MASK 0xc1c 91 92#define GT_PCI_MASK 0xc24 93 94#define GT_PCICFG_ADDR 0xcf8 95#define PCICFG_REG 0x000000ff 96#define PCICFG_FUNC 0x00000700 97#define PCICFG_DEV 0x0000f800 98#define PCICFG_BUS 0x00ff0000 99#define PCICFG_ENABLE 0x80000000 100 101#define GT_PCICFG_DATA 0xcfc 102