1/*	$NetBSD$	*/
2
3/*
4 * Copyright (c) 2003, 2005 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *	This product includes software developed for the NetBSD Project by
20 *	Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 *    or promote products derived from this software without specific prior
23 *    written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __PXA2X0_DMAC_H
39#define __PXA2X0_DMAC_H
40
41typedef u_int dmac_peripheral_t;
42#define DMAC_PERIPH_NONE    	(~0)
43#define DMAC_PERIPH_DREQ0    	0
44#define DMAC_PERIPH_DREQ1     	1
45#define DMAC_PERIPH_I2SRX     	2
46#define DMAC_PERIPH_I2STX     	3
47#define DMAC_PERIPH_BTUARTRX	4
48#define DMAC_PERIPH_BTUARTTX	5
49#define DMAC_PERIPH_FFUARTRX	6
50#define DMAC_PERIPH_FFUARTTX	7
51#define DMAC_PERIPH_AC97MIC	8
52#define DMAC_PERIPH_AC97MODEMRX	9
53#define DMAC_PERIPH_AC97MODEMTX	10
54#define DMAC_PERIPH_AC97AUDIORX 11
55#define DMAC_PERIPH_AC97AUDIOTX 12
56#define DMAC_PERIPH_SSPRX	13
57#define DMAC_PERIPH_SSPTX	14
58#define DMAC_PERIPH_FICPRX	17
59#define DMAC_PERIPH_FICPTX	18
60#define DMAC_PERIPH_STUARTRX	19
61#define DMAC_PERIPH_STUARTTX	20
62#define DMAC_PERIPH_MMCRX	21
63#define DMAC_PERIPH_MMCTX	22
64#define DMAC_PERIPH_USBEP(n)	(24+(n))   /* for endpoint 1..4,6..9,11..14 */
65#define	DMAC_N_PERIPH		40
66
67typedef enum {
68#define	DMAC_PRIORITY_NORMAL	DMAC_PRIORITY_LOW
69	DMAC_PRIORITY_LOW = 0,
70	DMAC_PRIORITY_MED,
71	DMAC_PRIORITY_HIGH
72} dmac_priority_t;
73
74typedef enum {
75	DMAC_FLOW_CTRL_NONE,
76	DMAC_FLOW_CTRL_SRC,
77	DMAC_FLOW_CTRL_DEST
78} dmac_flow_ctrl_t;
79
80typedef enum {
81	DMAC_DEV_WIDTH_DEFAULT = 0,
82	DMAC_DEV_WIDTH_1,
83	DMAC_DEV_WIDTH_2,
84	DMAC_DEV_WIDTH_4
85} dmac_dev_width_t;
86
87typedef enum {
88	DMAC_BURST_SIZE_8 = 1,
89	DMAC_BURST_SIZE_16,
90	DMAC_BURST_SIZE_32
91} dmac_burst_size_t;
92
93struct dmac_xfer_desc {
94	/*
95	 * Hold the source/destination address.
96	 * Note that if this is TRUE, then xd_nsegs must be at least '1',
97	 * and the first dma segment in xd_dma_segs must have a non-zero
98	 * ds_len field.
99	 */
100	bool xd_addr_hold;
101
102	u_int xd_nsegs;
103	bus_dma_segment_t *xd_dma_segs;
104};
105
106struct dmac_xfer {
107	/*
108	 * The following fields must be initialised by clients of the
109	 * DMAC driver.
110	 * The DMAC driver treats all these fields as Read-Only.
111	 */
112
113	/* Client-specific cookie for this request */
114	void *dx_cookie;
115
116	/* Client function to invoke when the transfer completes */
117	void (*dx_done)(struct dmac_xfer *, int);
118
119	/* Priority to assign to the transfer */
120	dmac_priority_t dx_priority;
121
122	/* Peripheral device involved in the transfer */
123	dmac_peripheral_t dx_peripheral;
124
125	/* Flow Control */
126	dmac_flow_ctrl_t dx_flow;
127
128	/* Device width */
129	dmac_dev_width_t dx_dev_width;
130
131	/* Burst size */
132	dmac_burst_size_t dx_burst_size;
133
134	/* Loop notification period */
135	size_t dx_loop_notify;
136/*
137 * Initialise dx_loop_notify to the following value if you do not
138 * need to use the looping facility of the DMA engine. (Looping is
139 * primarily for use by the AC97 driver, but may be of interest to
140 * other drivers...)
141 */
142#define	DMAC_DONT_LOOP	0
143
144	/* Source/Destination descriptors */
145	struct dmac_xfer_desc dx_desc[2];
146#define DMAC_DESC_SRC 0
147#define DMAC_DESC_DST 1
148};
149
150extern struct dmac_xfer *pxa2x0_dmac_allocate_xfer(void);
151extern void pxa2x0_dmac_free_xfer(struct dmac_xfer *);
152extern int pxa2x0_dmac_start_xfer(struct dmac_xfer *);
153extern void pxa2x0_dmac_abort_xfer(struct dmac_xfer *);
154
155#endif /* __PXA2X0_DMAC_H */
156