1/*	$NetBSD: ixp425_timer.c,v 1.20 2020/05/29 12:30:39 rin Exp $ */
2
3/*
4 * Copyright (c) 2003
5 *	Ichiro FUKUHARA <ichiro@ichiro.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
31__KERNEL_RCSID(0, "$NetBSD: ixp425_timer.c,v 1.20 2020/05/29 12:30:39 rin Exp $");
32
33#include "opt_ixp425.h"
34
35#include <sys/types.h>
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/kernel.h>
39#include <sys/atomic.h>
40#include <sys/time.h>
41#include <sys/timetc.h>
42#include <sys/device.h>
43
44#include <dev/clock_subr.h>
45
46#include <sys/bus.h>
47#include <machine/intr.h>
48
49#include <arm/cpufunc.h>
50
51#include <arm/xscale/ixp425reg.h>
52#include <arm/xscale/ixp425var.h>
53#include <arm/xscale/ixp425_sipvar.h>
54
55static int	ixpclk_match(device_t, cfdata_t, void *);
56static void	ixpclk_attach(device_t, device_t, void *);
57static u_int	ixpclk_get_timecount(struct timecounter *);
58
59static uint32_t counts_per_hz;
60
61static void *clock_ih;
62
63/* callback functions for intr_functions */
64int	ixpclk_intr(void *);
65
66struct ixpclk_softc {
67	bus_addr_t		sc_baseaddr;
68	bus_space_tag_t		sc_iot;
69	bus_space_handle_t      sc_ioh;
70};
71
72#ifndef IXP425_CLOCK_FREQ
73#define	COUNTS_PER_SEC		66666600	/* 66MHz */
74#else
75#define	COUNTS_PER_SEC		IXP425_CLOCK_FREQ
76#endif
77#define	COUNTS_PER_USEC		((COUNTS_PER_SEC / 1000000) + 1)
78
79static struct ixpclk_softc *ixpclk_sc;
80
81static struct timecounter ixpclk_timecounter = {
82	.tc_get_timecount = ixpclk_get_timecount,
83	.tc_counter_mask = 0xffffffff,
84	.tc_frequency = COUNTS_PER_SEC,
85	.tc_name = "ixpclk",
86	.tc_quality = 100,
87};
88
89static volatile uint32_t ixpclk_base;
90
91CFATTACH_DECL_NEW(ixpclk, sizeof(struct ixpclk_softc),
92		ixpclk_match, ixpclk_attach, NULL, NULL);
93
94#define GET_TIMER_VALUE(sc)	(bus_space_read_4((sc)->sc_iot,		\
95						  (sc)->sc_ioh,		\
96						  IXP425_OST_TIM0))
97
98#define GET_TS_VALUE(sc)	(*(volatile uint32_t *) \
99				  (IXP425_TIMER_VBASE + IXP425_OST_TS))
100
101static int
102ixpclk_match(device_t parent, cfdata_t match, void *aux)
103{
104	return 2;
105}
106
107static void
108ixpclk_attach(device_t parent, device_t self, void *aux)
109{
110	struct ixpclk_softc		*sc = device_private(self);
111	struct ixpsip_attach_args	*sa = aux;
112
113	printf("\n");
114
115	ixpclk_sc = sc;
116
117	sc->sc_iot = sa->sa_iot;
118	sc->sc_baseaddr = sa->sa_addr;
119
120	if (bus_space_map(sc->sc_iot, sa->sa_addr, sa->sa_size, 0,
121			  &sc->sc_ioh))
122		panic("%s: Cannot map registers", device_xname(self));
123
124	aprint_normal_dev(self, "IXP425 Interval Timer\n");
125}
126
127/*
128 * cpu_initclocks:
129 *
130 *	Initialize the clock and get them going.
131 */
132void
133cpu_initclocks(void)
134{
135	struct ixpclk_softc *sc = ixpclk_sc;
136	u_int oldirqstate;
137
138	if (hz < 50 || COUNTS_PER_SEC % hz) {
139		aprint_error("Cannot get %d Hz clock; using 100 Hz\n", hz);
140		hz = 100;
141	}
142
143	/*
144	 * We only have one timer available; stathz and profhz are
145	 * always left as 0 (the upper-layer clock code deals with
146	 * this situation).
147	 */
148	if (stathz != 0)
149		aprint_error("Cannot get %d Hz statclock\n", stathz);
150	stathz = 0;
151
152	if (profhz != 0)
153		aprint_error("Cannot get %d Hz profclock\n", profhz);
154	profhz = 0;
155
156	/* Report the clock frequency. */
157	aprint_normal("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz);
158
159	oldirqstate = disable_interrupts(I32_bit);
160
161	/* Hook up the clock interrupt handler. */
162	clock_ih = ixp425_intr_establish(IXP425_INT_TMR0, IPL_CLOCK,
163					 ixpclk_intr, NULL);
164	if (clock_ih == NULL)
165		panic("cpu_initclocks: unable to register timer interrupt");
166
167	/* Set up the new clock parameters. */
168
169	/* clear interrupt */
170	bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS,
171			  OST_WARM_RESET | OST_WDOG_INT | OST_TS_INT |
172			  OST_TIM1_INT | OST_TIM0_INT);
173
174	counts_per_hz = COUNTS_PER_SEC / hz;
175
176	/* reload value & Timer enable */
177	bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_TIM0_RELOAD,
178			  (counts_per_hz & TIMERRELOAD_MASK) | OST_TIMER_EN);
179
180	restore_interrupts(oldirqstate);
181
182	tc_init(&ixpclk_timecounter);
183}
184
185/*
186 * setstatclockrate:
187 *
188 *	Set the rate of the statistics clock.
189 *
190 *	We assume that hz is either stathz or profhz, and that neither
191 *	will change after being set by cpu_initclocks().  We could
192 *	recalculate the intervals here, but that would be a pain.
193 */
194void
195setstatclockrate(int newhz)
196{
197
198	/*
199	 * XXX Use TMR1?
200	 */
201}
202
203static u_int
204ixpclk_get_timecount(struct timecounter *tc)
205{
206	u_int	savedints, base, counter;
207
208	savedints = disable_interrupts(I32_bit);
209	base = ixpclk_base;
210	counter = GET_TIMER_VALUE(ixpclk_sc);
211	restore_interrupts(savedints);
212
213	return base - counter;
214}
215
216/*
217 * delay:
218 *
219 *	Delay for at least N microseconds.
220 */
221void
222delay(u_int n)
223{
224	uint32_t first, last;
225	int usecs;
226
227	if (n == 0)
228		return;
229
230	/*
231	 * Clamp the timeout at a maximum value (about 32 seconds with
232	 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
233	 * near that length of time and if they are, they should be hung
234	 * out to dry.
235	 */
236	if (n >= (0x80000000U / COUNTS_PER_USEC))
237		usecs = (0x80000000U / COUNTS_PER_USEC) - 1;
238	else
239		usecs = n * COUNTS_PER_USEC;
240
241	/* Note: Timestamp timer counts *up*, unlike the other timers */
242	first = GET_TS_VALUE();
243
244	while (usecs > 0) {
245		last = GET_TS_VALUE();
246		usecs -= (int)(last - first);
247		first = last;
248	}
249}
250
251/*
252 * ixpclk_intr:
253 *
254 *	Handle the hardclock interrupt.
255 */
256int
257ixpclk_intr(void *arg)
258{
259	struct ixpclk_softc *sc = ixpclk_sc;
260	struct clockframe *frame = arg;
261
262	bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS,
263			  OST_TIM0_INT);
264
265	atomic_add_32(&ixpclk_base, counts_per_hz);
266
267	hardclock(frame);
268
269	return (1);
270}
271