1/*	$NetBSD: ixp425_npevar.h,v 1.4 2012/10/14 14:20:58 msaitoh Exp $	*/
2
3/*-
4 * Copyright (c) 2006 Sam Leffler.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/arm/xscale/ixp425/ixp425_npevar.h,v 1.1 2006/11/19 23:55:23 sam Exp $
27 */
28
29#ifndef _IXP425_NPEVAR_H_
30#define _IXP425_NPEVAR_H_
31
32/*
33 * Intel (R) IXP400 Software NPE Image ID Definition
34 *
35 * Firmware Id's for current firmware image.  These are typed by
36 * NPE ID and the feature set.  Not all features are available
37 * on all NPE's.
38 *
39 * HSS-0: supports 32 channelized and 4 packetized.
40 * HSS-0 + ATM + SPHY:
41 *    For HSS, 16/32 channelized and 4/0 packetized.
42 *    For ATM, AAL5, AAL0 and OAM for UTOPIA SPHY, 1 logical port, 32 VCs.
43 *    Fast Path support.
44 * HSS-0 + ATM + MPHY:
45 *    For HSS, 16/32 channelized and 4/0 packetized.
46 *    For ATM, AAL5, AAL0 and OAM for UTOPIA MPHY, 1 logical port, 32 VCs.
47 *    Fast Path support.
48 * ATM-Only:
49 *    AAL5, AAL0 and OAM for UTOPIA MPHY, 12 logical ports, 32 VCs.
50 *    Fast Path support.
51 * HSS-2:
52 *    HSS-0 and HSS-1.
53 *    Each HSS port supports 32 channelized and 4 packetized.
54 * ETH: Ethernet Rx/Tx which includes:
55 *    MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
56 * ETH+VLAN Ethernet Rx/Tx which includes:
57 *    MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
58 * ETH+VLAN+HDR: Ethernet Rx/Tx which includes:
59 *    SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
60 */
61/* XXX not right, revise */
62/* NPE A Firmware Image Id's */
63#define	NPEFW_A_HSS0		0x00010000 /* HSS-0: 32 chan+4 packet */
64#define NPEFW_A_HSS0_ATM_S_1	0x00020000 /* HSS-0+ATM UTOPIA SPHY (1 port) */
65#define NPEFW_A_HSS0_ATM_M_1	0x00020000 /* HSS-0+ATM UTOPIA MPHY (1 port) */
66#define NPEFW_A_ATM_M_12	0x00040000 /* ATM UTOPIA MPHY (12 ports) */
67#define NPEFW_A_DMA		0x00150100 /* DMA only */
68#define	NPEFW_A_HSS2		0x00090000 /* HSS-0 + HSS-1 */
69#define	NPEFW_A_ETH		0x10800200 /* Basic Ethernet */
70#define	NPEFW_A_ETH_VLAN	0x10810200 /* NPEFW_A_ETH + VLAN QoS */
71#define	NPEFW_A_ETH_VLAN_HDR	0x10820200 /* NPEFW_A_ETH_VLAN + Hdr conv */
72/* XXX ... more not included */
73
74/* NPE B Firmware Image Id's */
75#define NPEFW_B_ETH		0x01000200 /* Basic Ethernet */
76#define NPEFW_B_ETH_VLAN	0x01010200 /* NPEFW_B_ETH + VLAN QoS */
77#define NPEFW_B_ETH_VLAN_HDR	0x01020201 /* NPEFW_B_ETH_VLAN + Hdr conv */
78#define NPEFW_B_DMA		0x01020100 /* DMA only */
79/* XXX ... more not include */
80
81#define	IXP425_NPE_B_IMAGEID	0x01000201
82#define	IXP425_NPE_C_IMAGEID	0x02000201
83
84struct ixpnpe_softc {
85	device_t	sc_dev;
86	bus_dma_tag_t	sc_dt;
87	bus_space_tag_t	sc_iot;
88	bus_space_handle_t sc_ioh;
89	bus_size_t	sc_size;	/* size of mapped register window */
90	int		sc_unit;
91	void		*sc_ih;		/* interrupt handler */
92	kmutex_t	sc_lock;	/* mailbox lock */
93	uint32_t	sc_msg[2];	/* reply msg collected in ixpnpe_intr */
94	int		sc_msgwaiting;	/* sc_msg holds valid data */
95
96	int		validImage;	/* valid ucode image loaded */
97	int		started;	/* NPE is started */
98	uint8_t		functionalityId;/* ucode functionality ID */
99	int		insMemSize;	/* size of instruction memory */
100	int		dataMemSize;	/* size of data memory */
101	uint32_t	savedExecCount;
102	uint32_t	savedEcsDbgCtxtReg2;
103	void		(*macresetcbfunc)(void *);
104	void		*macresetcbarg;
105};
106
107int	ixpnpe_stopandreset(struct ixpnpe_softc *);
108int	ixpnpe_start(struct ixpnpe_softc *);
109int	ixpnpe_stop(struct ixpnpe_softc *);
110int	ixpnpe_init(struct ixpnpe_softc *, const char *imageName,
111	    uint32_t imageId);
112int	ixpnpe_getfunctionality(struct ixpnpe_softc *sc);
113
114int	ixpnpe_sendmsg(struct ixpnpe_softc *, const uint32_t msg[2]);
115int	ixpnpe_recvmsg(struct ixpnpe_softc *, uint32_t msg[2]);
116int	ixpnpe_sendandrecvmsg(struct ixpnpe_softc *, const uint32_t send[2],
117	    uint32_t recv[2]);
118
119struct ixpnpe_attach_args {
120	int na_unit;
121	int na_phy;
122	struct ixpnpe_softc *na_npe;
123	bus_space_tag_t na_iot;
124	bus_dma_tag_t na_dt;
125};
126
127extern void (*npe_getmac_md)(int, uint8_t *);
128
129#endif /* _IXP425_NPEVAR_H_ */
130