1/* $NetBSD: zynq_usb.c,v 1.3 2021/08/07 16:18:46 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__KERNEL_RCSID(0, "$NetBSD: zynq_usb.c,v 1.3 2021/08/07 16:18:46 thorpej Exp $"); 31 32#include "opt_soc.h" 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/device.h> 38#include <sys/kernel.h> 39#include <sys/intr.h> 40#include <sys/systm.h> 41 42#include <dev/usb/usb.h> 43#include <dev/usb/usbdi.h> 44#include <dev/usb/usbdivar.h> 45#include <dev/usb/usb_mem.h> 46 47#include <dev/usb/ehcireg.h> 48#include <dev/usb/ehcivar.h> 49#include <dev/usb/ulpireg.h> 50 51#include <arm/xilinx/zynq_usbreg.h> 52#include <arm/xilinx/zynq_usbvar.h> 53 54#include "locators.h" 55 56static uint8_t ulpi_read(struct zynqehci_softc *sc, int addr); 57static void ulpi_write(struct zynqehci_softc *sc, int addr, uint8_t data); 58static void ulpi_reset(struct zynqehci_softc *sc); 59 60static void zynqusb_select_interface(struct zynqehci_softc *, enum zynq_usb_if); 61static void zynqusb_init(struct ehci_softc *); 62static void zynqusb_reset(struct zynqehci_softc *); 63 64void 65zynqusb_attach_common(device_t parent, device_t self, bus_space_tag_t iot, 66 bus_dma_tag_t dmat, paddr_t iobase, size_t size, int flags, 67 enum zynq_usb_if type, enum zynq_usb_role role) 68{ 69 struct zynqehci_softc *sc = device_private(self); 70 ehci_softc_t *hsc = &sc->sc_hsc; 71 uint16_t hcirev; 72 uint32_t id, hwhost, hwdevice; 73 const char *comma; 74 75 sc->sc_hsc.sc_dev = self; 76 sc->sc_iot = sc->sc_hsc.iot = iot; 77 sc->sc_iftype = type; 78 sc->sc_role = role; 79 80 hsc->sc_bus.ub_hcpriv = sc; 81 hsc->sc_bus.ub_revision = USBREV_2_0; 82 hsc->sc_flags |= EHCIF_ETTF; 83 hsc->sc_vendor_init = zynqusb_init; 84 85 aprint_normal("\n"); 86 87 if (bus_space_map(iot, iobase, size, 0, &sc->sc_ioh)) { 88 89 aprint_error_dev(self, "unable to map device\n"); 90 return; 91 } 92 93 if (bus_space_subregion(iot, sc->sc_ioh, 94 ZYNQUSB_EHCIREGS, ZYNQUSB_EHCI_SIZE - ZYNQUSB_EHCIREGS, 95 &sc->sc_hsc.ioh)) { 96 97 aprint_error_dev(self, "unable to map subregion\n"); 98 return; 99 } 100 101 id = bus_space_read_4(iot, sc->sc_ioh, ZYNQUSB_ID); 102 hcirev = bus_space_read_2(iot, sc->sc_hsc.ioh, EHCI_HCIVERSION); 103 104 aprint_normal_dev(self, 105 "Zynq USB Controller id=%d revision=%d version=%d\n", 106 (int)__SHIFTOUT(id, ZYNQUSB_ID_ID), 107 (int)__SHIFTOUT(id, ZYNQUSB_ID_REVISION), 108 (int)__SHIFTOUT(id, ZYNQUSB_ID_VERSION)); 109 aprint_normal_dev(self, "HCI revision=0x%x\n", hcirev); 110 111 hwhost = bus_space_read_4(iot, sc->sc_ioh, ZYNQUSB_HWHOST); 112 hwdevice = bus_space_read_4(iot, sc->sc_ioh, ZYNQUSB_HWDEVICE); 113 114 aprint_normal_dev(self, ""); 115 116 comma = ""; 117 if (hwhost & HWHOST_HC) { 118 int n_ports = 1 + __SHIFTOUT(hwhost, HWHOST_NPORT); 119 aprint_normal("%d host port%s", 120 n_ports, n_ports > 1 ? "s" : ""); 121 comma = ", "; 122 } 123 124 if (hwdevice & HWDEVICE_DC) { 125 int n_endpoints = __SHIFTOUT(hwdevice, HWDEVICE_DEVEP); 126 aprint_normal("%sdevice capable, %d endpoint%s", 127 comma, 128 n_endpoints, n_endpoints > 1 ? "s" : ""); 129 } 130 aprint_normal("\n"); 131 132 sc->sc_hsc.sc_bus.ub_dmatag = dmat; 133 134 sc->sc_hsc.sc_offs = bus_space_read_1(iot, sc->sc_hsc.ioh, 135 EHCI_CAPLENGTH); 136 137 zynqusb_reset(sc); 138 zynqusb_select_interface(sc, sc->sc_iftype); 139 140 if (sc->sc_iftype == ZYNQUSBC_IF_ULPI) { 141 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW, 0); 142 143 aprint_normal_dev(hsc->sc_dev, 144 "ULPI phy VID 0x%04x PID 0x%04x\n", 145 (ulpi_read(sc, ULPI_VENDOR_ID_LOW) | 146 ulpi_read(sc, ULPI_VENDOR_ID_HIGH) << 8), 147 (ulpi_read(sc, ULPI_PRODUCT_ID_LOW) | 148 ulpi_read(sc, ULPI_PRODUCT_ID_HIGH) << 8)); 149 150 ulpi_reset(sc); 151 } 152 153 if (sc->sc_iftype == ZYNQUSBC_IF_ULPI) { 154 if (hsc->sc_bus.ub_revision == USBREV_2_0) { 155 ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_CLEAR, 156 FUNCTION_CONTROL_XCVRSELECT); 157 ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_SET, 158 FUNCTION_CONTROL_TERMSELECT); 159 } else { 160 ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_SET, 161 XCVRSELECT_FSLS); 162 ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_CLEAR, 163 FUNCTION_CONTROL_TERMSELECT); 164 } 165 166 ulpi_write(sc, ULPI_OTG_CONTROL + ULPI_REG_SET, 167 OTG_CONTROL_USEEXTVBUSIND | 168 OTG_CONTROL_DRVVBUSEXT | 169 OTG_CONTROL_DRVVBUS | 170 OTG_CONTROL_CHRGVBUS); 171 } 172 173 /* Disable interrupts, so we don't get any spurious ones. */ 174 EOWRITE4(hsc, EHCI_USBINTR, 0); 175 176 /*intr_establish(intr, IPL_USB, IST_LEVEL, ehci_intr, hsc);*/ 177 178 int err = ehci_init(hsc); 179 if (err) { 180 aprint_error_dev(self, "init failed, error = %d\n", err); 181 return; 182 } 183 184 /* Attach usb device. */ 185 hsc->sc_child = config_found(self, &hsc->sc_bus, usbctlprint, 186 CFARGS_NONE); 187} 188 189static void 190zynqusb_select_interface(struct zynqehci_softc *sc, enum zynq_usb_if interface) 191{ 192 uint32_t reg; 193 struct ehci_softc *hsc = &sc->sc_hsc; 194 195 reg = EOREAD4(hsc, EHCI_PORTSC(1)); 196 reg &= ~(PORTSC_PTS | PORTSC_PTW); 197 switch (interface) { 198 case ZYNQUSBC_IF_UTMI_WIDE: 199 reg |= PORTSC_PTW_16; 200 case ZYNQUSBC_IF_UTMI: 201 reg |= PORTSC_PTS_UTMI; 202 break; 203 case ZYNQUSBC_IF_PHILIPS: 204 reg |= PORTSC_PTS_PHILIPS; 205 break; 206 case ZYNQUSBC_IF_ULPI: 207 reg |= PORTSC_PTS_ULPI; 208 break; 209 case ZYNQUSBC_IF_SERIAL: 210 reg |= PORTSC_PTS_SERIAL; 211 break; 212 } 213 EOWRITE4(hsc, EHCI_PORTSC(1), reg); 214} 215 216static uint32_t 217ulpi_wakeup(struct zynqehci_softc *sc, int tout) 218{ 219 uint32_t ulpi_view; 220 int i = 0; 221 ulpi_view = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW); 222 223 if ( !(ulpi_view & ULPI_SS) ) { 224 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 225 ZYNQUSB_ULPIVIEW, ULPI_WU); 226 for (i = 0; (tout < 0) || (i < tout); i++) { 227 ulpi_view = bus_space_read_4(sc->sc_iot, 228 sc->sc_ioh, ZYNQUSB_ULPIVIEW); 229 if ( !(ulpi_view & ULPI_WU) ) 230 break; 231 delay(1); 232 }; 233 } 234 235 if ((tout > 0) && (i >= tout)) { 236 aprint_error_dev(sc->sc_hsc.sc_dev, "%s: timeout\n", __func__); 237 } 238 239 return ulpi_view; 240} 241 242static uint32_t 243ulpi_wait(struct zynqehci_softc *sc, int tout) 244{ 245 uint32_t ulpi_view; 246 int i; 247 ulpi_view = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW); 248 249 for (i = 0; (tout < 0) | (i < tout); i++) { 250 ulpi_view = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 251 ZYNQUSB_ULPIVIEW); 252 if (!(ulpi_view & ULPI_RUN)) 253 break; 254 delay(1); 255 } 256 257 if ((tout > 0) && (i >= tout)) { 258 aprint_error_dev(sc->sc_hsc.sc_dev, "%s: timeout\n", __func__); 259 } 260 261 return ulpi_view; 262} 263 264#define TIMEOUT 100000 265 266static uint8_t 267ulpi_read(struct zynqehci_softc *sc, int addr) 268{ 269 uint32_t data; 270 271 ulpi_wakeup(sc, TIMEOUT); 272 273 data = ULPI_RUN | __SHIFTIN(addr, ULPI_ADDR); 274 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW, data); 275 276 data = ulpi_wait(sc, TIMEOUT); 277 278 return __SHIFTOUT(data, ULPI_DATRD); 279} 280 281static void 282ulpi_write(struct zynqehci_softc *sc, int addr, uint8_t data) 283{ 284 uint32_t reg; 285 286 ulpi_wakeup(sc, TIMEOUT); 287 288 reg = ULPI_RUN | ULPI_RW | __SHIFTIN(addr, ULPI_ADDR) | __SHIFTIN(data, ULPI_DATWR); 289 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW, reg); 290 291 ulpi_wait(sc, TIMEOUT); 292 293 return; 294} 295 296static void 297ulpi_reset(struct zynqehci_softc *sc) 298{ 299 uint8_t data; 300 int timo = 1000 * 1000; /* XXXX: 1sec */ 301 302 ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_SET, 303 FUNCTION_CONTROL_RESET /*0x20*/); 304 do { 305 data = ulpi_read(sc, ULPI_FUNCTION_CONTROL); 306 if (!(data & FUNCTION_CONTROL_RESET)) 307 break; 308 delay(100); 309 timo -= 100; 310 } while (timo > 0); 311 if (timo <= 0) { 312 aprint_error_dev(sc->sc_hsc.sc_dev, "%s: reset failed!!\n", 313 __func__); 314 return; 315 } 316 317 return; 318} 319 320static void 321zynqusb_reset(struct zynqehci_softc *sc) 322{ 323 uint32_t reg; 324 int i; 325 struct ehci_softc *hsc = &sc->sc_hsc; 326#define RESET_TIMEOUT 100 327 reg = EOREAD4(hsc, EHCI_USBCMD); 328 reg &= ~EHCI_CMD_RS; 329 EOWRITE4(hsc, EHCI_USBCMD, reg); 330 331 for (i=0; i < RESET_TIMEOUT; ++i) { 332 reg = EOREAD4(hsc, EHCI_USBCMD); 333 if ((reg & EHCI_CMD_RS) == 0) 334 break; 335 usb_delay_ms(&hsc->sc_bus, 1); 336 } 337 338 EOWRITE4(hsc, EHCI_USBCMD, reg | EHCI_CMD_HCRESET); 339 for (i = 0; i < RESET_TIMEOUT; i++) { 340 reg = EOREAD4(hsc, EHCI_USBCMD); 341 if ((reg & EHCI_CMD_HCRESET) == 0) 342 break; 343 usb_delay_ms(&hsc->sc_bus, 1); 344 } 345 if (i >= RESET_TIMEOUT) { 346 aprint_error_dev(hsc->sc_dev, "reset timeout (%x)\n", reg); 347 } 348 349 usb_delay_ms(&hsc->sc_bus, 100); 350} 351 352static void 353zynqusb_init(struct ehci_softc *hsc) 354{ 355 struct zynqehci_softc *sc = device_private(hsc->sc_dev); 356 uint32_t reg; 357 358 reg = EOREAD4(hsc, EHCI_PORTSC(1)); 359 reg &= ~(EHCI_PS_CSC | EHCI_PS_PEC | EHCI_PS_OCC); 360 reg |= EHCI_PS_PP | EHCI_PS_PE; 361 EOWRITE4(hsc, EHCI_PORTSC(1), reg); 362 363 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_OTGSC); 364 reg |= OTGSC_IDPU; 365 reg |= OTGSC_DPIE | OTGSC_IDIE; 366 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_OTGSC, reg); 367 368 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_USBMODE); 369 reg &= ~USBMODE_CM; 370 reg |= USBMODE_CM_HOST; 371 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_USBMODE, reg); 372} 373