1/* $NetBSD: sun50i_h6_gpio.c,v 1.4 2021/11/10 17:38:11 jakllsch Exp $ */ 2 3/*- 4 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__KERNEL_RCSID(0, "$NetBSD: sun50i_h6_gpio.c,v 1.4 2021/11/10 17:38:11 jakllsch Exp $"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/types.h> 36 37#include <arm/sunxi/sunxi_gpio.h> 38 39static const struct sunxi_gpio_pins h6_pins[] = { 40 { "PC0", 2, 0, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } }, 41 { "PC1", 2, 1, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 42 { "PC2", 2, 2, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } }, 43 { "PC3", 2, 3, { "gpio_in", "gpio_out", "nand", NULL, "spi0" } }, 44 { "PC4", 2, 4, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 45 { "PC5", 2, 5, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } }, 46 { "PC6", 2, 6, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } }, 47 { "PC7", 2, 7, { "gpio_in", "gpio_out", "nand", "mmc2", "spi0" } }, 48 { "PC8", 2, 8, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 49 { "PC9", 2, 9, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 50 { "PC10", 2, 10, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 51 { "PC11", 2, 11, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 52 { "PC12", 2, 12, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 53 { "PC13", 2, 13, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 54 { "PC14", 2, 14, { "gpio_in", "gpio_out", "nand", "mmc2" } }, 55 { "PC15", 2, 15, { "gpio_in", "gpio_out", "nand" } }, 56 { "PC16", 2, 16, { "gpio_in", "gpio_out", "nand" } }, 57 58 { "PD0", 3, 0, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 59 { "PD1", 3, 1, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 60 { "PD2", 3, 2, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 61 { "PD3", 3, 3, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 62 { "PD4", 3, 4, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 63 { "PD5", 3, 5, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 64 { "PD6", 3, 6, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 65 { "PD7", 3, 7, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 66 { "PD8", 3, 8, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 67 { "PD9", 3, 9, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 68 { "PD10", 3, 10, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 69 { "PD11", 3, 11, { "gpio_in", "gpio_out", "lcd0", "ts0", "csi", "emac" } }, 70 { "PD12", 3, 12, { "gpio_in", "gpio_out", "lcd0", "ts1", "csi", "emac" } }, 71 { "PD13", 3, 13, { "gpio_in", "gpio_out", "lcd0", "ts1", "csi", "emac" } }, 72 { "PD14", 3, 14, { "gpio_in", "gpio_out", "lcd0", "ts1", "dmic", "csi" } }, 73 { "PD15", 3, 15, { "gpio_in", "gpio_out", "lcd0", "ts1", "dmic", "csi" } }, 74 { "PD16", 3, 16, { "gpio_in", "gpio_out", "lcd0", "ts1", "dmic" } }, 75 { "PD17", 3, 17, { "gpio_in", "gpio_out", "lcd0", "ts2", "dmic" } }, 76 { "PD18", 3, 18, { "gpio_in", "gpio_out", "lcd0", "ts2", "dmic" } }, 77 { "PD19", 3, 19, { "gpio_in", "gpio_out", "lcd0", "ts2", "uart2", "emac" } }, 78 { "PD20", 3, 20, { "gpio_in", "gpio_out", "lcd0", "ts2", "uart2", "emac" } }, 79 { "PD21", 3, 21, { "gpio_in", "gpio_out", "lcd0", "ts2", "uart2" } }, 80 { "PD22", 3, 22, { "gpio_in", "gpio_out", "pwm0", "ts3", "uart2" } }, 81 { "PD23", 3, 23, { "gpio_in", "gpio_out", "i2c2", "ts3", "uart3", "jtag" } }, 82 { "PD24", 3, 24, { "gpio_in", "gpio_out", "i2c2", "ts3", "uart3", "jtag" } }, 83 { "PD25", 3, 25, { "gpio_in", "gpio_out", "i2c0", "ts3", "uart3", "jtag" } }, 84 { "PD26", 3, 26, { "gpio_in", "gpio_out", "i2c0", "ts3", "uart3", "jtag" } }, 85 86 { "PF0", 5, 0, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 87 { "PF1", 5, 1, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 88 { "PF2", 5, 2, { "gpio_in", "gpio_out", "mmc0", "uart0" } }, 89 { "PF3", 5, 3, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 90 { "PF4", 5, 4, { "gpio_in", "gpio_out", "mmc0", "uart0" } }, 91 { "PF5", 5, 5, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 92 { "PF6", 5, 6, { "gpio_in", "gpio_out" } }, 93 94 { "PG0", 6, 0, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 0 }, 95 { "PG1", 6, 1, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 1 }, 96 { "PG2", 6, 2, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 2 }, 97 { "PG3", 6, 3, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 3 }, 98 { "PG4", 6, 4, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 4 }, 99 { "PG5", 6, 5, { "gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "irq" }, 6, 5 }, 100 { "PG6", 6, 6, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "irq" }, 6, 6 }, 101 { "PG7", 6, 7, { "gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "irq" }, 6, 7 }, 102 { "PG8", 6, 8, { "gpio_in", "gpio_out", "uart1", "sim0", NULL, NULL, "irq" }, 6, 8 }, 103 { "PG9", 6, 9, { "gpio_in", "gpio_out", "uart1", "sim0", NULL, NULL, "irq" }, 6, 9 }, 104 { "PG10", 6, 10, { "gpio_in", "gpio_out", "i2s2", "h_i2s2", "sim0", NULL, "irq" }, 6, 10 }, 105 { "PG11", 6, 11, { "gpio_in", "gpio_out", "i2s2", "h_i2s2", "sim0", NULL, "irq" }, 6, 11 }, 106 { "PG12", 6, 12, { "gpio_in", "gpio_out", "i2s2", "h_i2s2", "sim0", NULL, "irq" }, 6, 12 }, 107 { "PG13", 6, 13, { "gpio_in", "gpio_out", "i2s2", "h_i2s2", "sim0", NULL, "irq" }, 6, 13 }, 108 { "PG14", 6, 14, { "gpio_in", "gpio_out", "i2s2", "h_i2s2", "sim0", NULL, "irq" }, 6, 13 }, 109 110 { "PH0", 7, 0, { "gpio_in", "gpio_out", "uart0", "i2s0", "h_i2s0", "sim1", "irq" }, 6, 0 }, 111 { "PH1", 7, 1, { "gpio_in", "gpio_out", "uart0", "i2s0", "h_i2s0", "sim1", "irq" }, 6, 1 }, 112 { "PH2", 7, 2, { "gpio_in", "gpio_out", "cir", "i2s0", "h_i2s0", "sim1", "irq" }, 6, 2 }, 113 { "PH3", 7, 3, { "gpio_in", "gpio_out", "spi1", "i2s0", "h_i2s0", "sim1", "irq" }, 6, 3 }, 114 { "PH4", 7, 4, { "gpio_in", "gpio_out", "spi1", "i2s0", "h_i2s0", "sim1", "irq" }, 6, 4 }, 115 { "PH5", 7, 5, { "gpio_in", "gpio_out", "spi1", "spdif", "i2c1", "sim1", "irq" }, 6, 5 }, 116 { "PH6", 7, 6, { "gpio_in", "gpio_out", "spi1", "spdif", "i2c1", "sim1", "irq" }, 6, 6 }, 117 { "PH7", 7, 7, { "gpio_in", "gpio_out", NULL, "spdif", NULL, NULL, "irq" }, 6, 7 }, 118 { "PH8", 7, 8, { "gpio_in", "gpio_out", "hdmi", NULL, NULL, NULL, "irq" }, 6, 8 }, 119 { "PH9", 7, 9, { "gpio_in", "gpio_out", "hdmi", NULL, NULL, NULL, "irq" }, 6, 9 }, 120 { "PH10", 7, 10, { "gpio_in", "gpio_out", "hdmi", NULL, NULL, NULL, "irq" }, 6, 10 }, 121}; 122 123static const struct sunxi_gpio_pins h6_r_pins[] = { 124 { "PL0", 0, 0, { "gpio_in", "gpio_out", "s_rsb", "s_i2c", NULL, NULL, "irq" }, 6, 0 }, 125 { "PL1", 0, 1, { "gpio_in", "gpio_out", "s_rsb", "s_i2c", NULL, NULL, "irq" }, 6, 1 }, 126 { "PL2", 0, 2, { "gpio_in", "gpio_out", "s_uart", NULL, NULL, NULL, "irq" }, 6, 2 }, 127 { "PL3", 0, 3, { "gpio_in", "gpio_out", "s_uart", NULL, NULL, NULL, "irq" }, 6, 3 }, 128 { "PL4", 0, 4, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "irq" }, 6, 4 }, 129 { "PL5", 0, 5, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "irq" }, 6, 5 }, 130 { "PL6", 0, 6, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "irq" }, 6, 6 }, 131 { "PL7", 0, 7, { "gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "irq" }, 6, 7 }, 132 { "PL8", 0, 8, { "gpio_in", "gpio_out", "s_i2s", NULL, NULL, NULL, "irq" }, 6, 8 }, 133 { "PL9", 0, 9, { "gpio_in", "gpio_out", "s_cir_rx", NULL, NULL, NULL, "irq" }, 6, 9 }, 134 { "PL10", 0, 10, { "gpio_in", "gpio_out", "s_spdif", NULL, NULL, NULL, "irq" }, 6, 10 }, 135 136 { "PM0", 1, 0, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "irq" }, 6, 0 }, 137 { "PM1", 1, 1, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "irq" }, 6, 1 }, 138 { "PM2", 1, 2, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "irq" }, 6, 2 }, 139 { "PM3", 1, 3, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "irq" }, 6, 3 }, 140 { "PM4", 1, 4, { "gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "irq" }, 6, 4 }, 141}; 142 143const struct sunxi_gpio_padconf sun50i_h6_padconf = { 144 .npins = __arraycount(h6_pins), 145 .pins = h6_pins, 146}; 147 148const struct sunxi_gpio_padconf sun50i_h6_r_padconf = { 149 .npins = __arraycount(h6_r_pins), 150 .pins = h6_r_pins, 151}; 152