1/* $NetBSD: exynos_var.h,v 1.29 2021/01/18 02:35:49 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by Reinoud Zandijk. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#ifndef _ARM_SAMSUNG_EXYNOS_VAR_H_ 36#define _ARM_SAMSUNG_EXYNOS_VAR_H_ 37 38#include <sys/types.h> 39#include <sys/bus.h> 40#include <sys/gpio.h> 41#include <dev/gpio/gpiovar.h> 42#include <arm/samsung/exynos_reg.h> 43 44extern uint32_t exynos_soc_id; 45extern uint32_t exynos_pop_id; 46 47#define EXYNOS_PRODUCT_FAMILY(soc) __SHIFTOUT((soc), __BITS(24,31)) 48#define EXYNOS4_PRODUCT_FAMILY 0xe4 49#define EXYNOS5_PRODUCT_FAMILY 0xe5 50#define EXYNOS_PRODUCT_ID(soc) __SHIFTOUT((soc), __BITS(12,31)) 51#define EXYNOS_PRODUCT_PACKAGE(soc) __SHIFTOUT((soc), __BITS(8,11)) 52#define EXYNOS_PRODUCT_REV(soc) __SHIFTOUT((soc), __BITS(4,7)) 53#define EXYNOS_PRODUCT_SUBREV(soc) __SHIFTOUT((soc), __BITS(0,3)) 54 55 56#define IS_EXYNOS4410_P() (EXYNOS_PRODUCT_ID(exynos_soc_id) == 0xe4410) 57#define IS_EXYNOS4412_P() (EXYNOS_PRODUCT_ID(exynos_soc_id) == 0xe4412) 58#define IS_EXYNOS4412_R0_P() \ 59 ((EXYNOS_PRODUCT_ID(exynos_soc_id) == 0xe4412) && \ 60 (EXYNOS_PRODUCT_REV(exynos_soc_id) == 0)) 61#define IS_EXYNOS4X12_P() ((EXYNOS_PRODUCT_ID(exynos_soc_id) & 0xff0ff) \ 62 == 0xe4012) 63 64#define IS_EXYNOS4_P() (EXYNOS_PRODUCT_FAMILY(exynos_soc_id) == EXYNOS4_PRODUCT_FAMILY) 65 66#define IS_EXYNOS5410_P() (EXYNOS_PRODUCT_ID(exynos_soc_id) == 0xe5410) 67#define IS_EXYNOS5422_P() (EXYNOS_PRODUCT_ID(exynos_soc_id) == 0xe5422) 68#define IS_EXYNOS5440_P() (EXYNOS_PRODUCT_ID(exynos_soc_id) == 0xe5440) 69 70#define IS_EXYNOS5_P() (EXYNOS_PRODUCT_FAMILY(exynos_soc_id) == EXYNOS5_PRODUCT_FAMILY) 71 72 73struct exyo_locators { 74 const char *loc_name; 75 bus_size_t loc_offset; 76 bus_size_t loc_size; 77 int loc_port; 78 int loc_intr; 79 int loc_flags; 80 81 /* for i2c: */ 82 const char *loc_gpio_bus; 83 uint8_t loc_sda, loc_slc, loc_func; 84}; 85 86 87struct exyo_attach_args { 88 struct exyo_locators exyo_loc; 89 bus_space_tag_t exyo_core_bst; 90 bus_space_tag_t exyo_core_a4x_bst; 91 bus_space_handle_t exyo_core_bsh; 92 bus_dma_tag_t exyo_dmat; 93 bus_dma_tag_t exyo_coherent_dmat; 94}; 95 96struct exynos_pinctrl_banks { 97 struct exynos_gpio_bank *epb_banks; 98 size_t epb_nbanks; 99}; 100 101struct exynos_gpio_pinset { 102 char pinset_bank[10]; 103 uint8_t pinset_func; 104 uint8_t pinset_mask; 105}; 106 107struct exynos_gpio_pindata { 108 gpio_chipset_tag_t pd_gc; 109 int pd_pin; 110}; 111 112struct exynos_gpio_pin_cfg { 113 uint32_t cfg; 114 int cfg_valid; 115 uint32_t pud; 116 int pud_valid; 117 uint32_t drv; 118 int drv_valid; 119 uint32_t conpwd; 120 int conpwd_valid; 121 uint32_t pudpwd; 122 int pudpwd_valid; 123}; 124 125struct exynos_gpio_softc { 126 device_t sc_dev; 127 bus_space_tag_t sc_bst; 128 bus_space_handle_t sc_bsh; 129 struct exynos_gpio_bank *sc_bank; 130 int sc_phandle; 131}; 132 133#define EXYNOS_MAX_IIC_BUSSES 9 134struct i2c_controller; 135extern struct i2c_controller *exynos_i2cbus[EXYNOS_MAX_IIC_BUSSES]; 136 137 138extern struct bus_space exynos_bs_tag; 139extern struct bus_space exynos_a4x_bs_tag; 140extern struct arm32_bus_dma_tag exynos_bus_dma_tag; 141extern struct arm32_bus_dma_tag exynos_coherent_bus_dma_tag; 142 143extern struct bus_space armv7_generic_bs_tag; 144extern struct bus_space armv7_generic_a4x_bs_tag; 145extern bus_space_handle_t exynos_core_bsh; 146extern bus_space_handle_t exynos_wdt_bsh; 147extern bus_space_handle_t exynos_pmu_bsh; 148extern bus_space_handle_t exynos_cmu_bsh; 149extern bus_space_handle_t exynos_sysreg_bsh; 150 151extern void exynos_bootstrap(int); 152extern void exynos_dma_bootstrap(psize_t memsize); 153 154struct exynos_pinctrl_softc; 155struct exynos_gpio_softc; 156struct fdt_attach_args; 157 158extern struct exynos_gpio_softc * exynos_gpio_bank_config(struct exynos_pinctrl_softc *, 159 const struct fdt_attach_args *, int); 160extern void exynos_wdt_reset(void); 161 162extern void exynos_init_clkout_for_usb(void); // board specific 163 164extern void exynos_clocks_bootstrap(void); 165extern void exynos_sysctl_cpufreq_init(void); 166extern uint64_t exynos_get_cpufreq(void); 167 168extern void exynos_device_register(device_t self, void *aux); 169extern void exynos_device_register_post_config(device_t self, void *aux); 170extern void exynos_usb_phy_init(bus_space_handle_t usb2phy_bsh); 171extern void exynos_usb_soc_powerup(void); 172 173extern void exyo_device_register(device_t self, void *aux); 174extern void exyo_device_register_post_config(device_t self, void *aux); 175 176extern struct exynos_pinctrl_banks exynos5410_pinctrl_banks; 177extern struct exynos_pinctrl_banks exynos5420_pinctrl_banks; 178 179extern struct exynos_gpio_bank *exynos_gpio_bank_lookup(const struct exynos_pinctrl_banks *, const char *name); 180extern bool exynos_gpio_pinset_available(const struct exynos_gpio_pinset *); 181extern void exynos_gpio_pinset_acquire(const struct exynos_gpio_pinset *); 182extern void exynos_gpio_pinset_release(const struct exynos_gpio_pinset *); 183extern void exynos_gpio_pinset_to_pindata(const struct exynos_gpio_pinset *, 184 int pinnr, struct exynos_gpio_pindata *); 185extern bool exynos_gpio_pin_reserve(const char *, struct exynos_gpio_pindata *); 186extern void exynos_gpio_pin_ctl_write(const struct exynos_gpio_bank *, 187 const struct exynos_gpio_pin_cfg *, 188 int); 189static inline void 190exynos_gpio_pindata_write(const struct exynos_gpio_pindata *pd, int value) 191{ 192 gpiobus_pin_write(pd->pd_gc, pd->pd_pin, value); 193} 194 195static inline int 196exynos_gpio_pindata_read(const struct exynos_gpio_pindata *pd) 197{ 198 return gpiobus_pin_read(pd->pd_gc, pd->pd_pin); 199} 200 201static inline void 202exynos_gpio_pindata_ctl(const struct exynos_gpio_pindata *pd, int flags) 203{ 204 gpiobus_pin_ctl(pd->pd_gc, pd->pd_pin, flags); 205} 206 207 208#ifdef ARM_TRUSTZONE_FIRMWARE 209/* trustzone calls */ 210extern int exynos_do_idle(void); 211extern int exynos_set_cpu_boot_addr(int cpu, vaddr_t boot_addr); 212extern int exynos_cpu_boot(int cpu); 213#ifdef EXYNOS4 214extern int exynos4_l2cc_init(void); 215#endif 216#endif 217 218#endif /* _ARM_SAMSUNG_EXYNOS_VAR_H_ */ 219