1/* $NetBSD: exynos_reg.h,v 1.16 2024/06/02 13:28:45 andvar Exp $ */ 2 3/*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _ARM_SAMSUNG_EXYNOS_REG_H_ 33#define _ARM_SAMSUNG_EXYNOS_REG_H_ 34 35/* 36 * 37 * The exynos can boot from its iROM or from an external Nand memory. Since 38 * these are normally hardly used they are excluded from the normal register 39 * space here. 40 * 41 * XXX What about the audio subsystem region. Where are the docs? 42 * 43 * EXYNOS_CORE_PBASE points to the main SFR region. 44 * 45 * Notes: 46 * 47 * SFR Special Function Register 48 * ISP In-System Programming, like a JTAG 49 * ACP Accelerator Coherency Port 50 * SSS Security Sub System 51 * GIC Generic Interrupt Controller 52 * PMU Power Management Unit 53 * DMC 2D Graphics engine 54 * LEFTBUS Data bus / Peripheral bus 55 * RIGHTBUS ,, 56 * G3D 3D Graphics engine 57 * MFC Multi-Format Codec 58 * LCD0 LCD display 59 * MCT Multi Core Timer 60 * CMU Clock Management Unit 61 * TMU Thermal Management Unit 62 * PPMU Pin Parametric Measurement Unit (?) 63 * MMU Memory Management Unit 64 * MCTimer ? 65 * WDT Watch Dog Timer 66 * RTC Real Time Clock 67 * KEYIF Keypad interface 68 * SECKEY ? 69 * TZPC TrustZone Protection Controller 70 * UART Universal asynchronous receiver/transmitter 71 * I2C Inter IC Connect 72 * SPI Serial Peripheral Interface Bus 73 * I2S Inter-IC Sound, Integrated Interchip Sound, or IIS 74 * PCM Pulse-code modulation, audio stream at set fixed rate 75 * SPDIF Sony/Philips Digital Interface Format 76 * Slimbus Serial Low-power Inter-chip Media Bus 77 * SMMU System mmu. No idea as how its programmed (or not) 78 * PERI-L UART, I2C, SPI, I2S, PCM, SPDIF, PWM, I2CHDMI, Slimbus 79 * PERI-R CHIPID, SYSREG, PMU/CMU/TMU Bus I/F, MCTimer, WDT, RTC, KEYIF, 80 * SECKEY, TZPC 81 */ 82 83/* 84 * Common to Exynos4 and Exynos 5 85 * */ 86#define EXYNOS_CORE_PBASE 0x10000000 /* SFR */ 87#define EXYNOS_CORE_SIZE 0x10000000 88 89 90#define EXYNOS_CHIPID_OFFSET 0x00000000 91#define EXYNOS_PROD_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 0) 92#define EXYNOS_PACKAGE_ID_OFFSET (EXYNOS_CHIPID_OFFSET + 4) 93 94#define EXYNOS_PACKAGE_ID_2_GIG 0x06030058 95 96/* standard block size for offsets defined below */ 97#define EXYNOS_BLOCK_SIZE 0x00010000 98 99 100#if defined(SOC_EXYNOS5) 101#include <arm/samsung/exynos5_reg.h> 102#endif 103#if defined(SOC_EXYNOS4) 104#include <arm/samsung/exynos4_reg.h> 105#endif 106 107 108/* standard frequency settings */ 109#define EXYNOS_ACLK_REF_FREQ (200*1000*1000) /* 200 Mhz */ 110#define EXYNOS_UART_FREQ (109*1000*1000) /* should be EXYNOS_ACLK_REF_FREQ! */ 111 112#define EXYNOS_F_IN_FREQ (24*1000*1000) /* 24 Mhz */ 113#define EXYNOS_USB_FREQ EXYNOS_F_IN_FREQ/* 24 Mhz */ 114 115 116/* PLLs */ 117#define PLL_LOCK_OFFSET 0x000 118#define PLL_CON0_OFFSET 0x100 119#define PLL_CON1_OFFSET 0x104 120 121#define PLL_CON0_ENABLE __BIT(31) 122#define PLL_CON0_LOCKED __BIT(29) /* has the PLL locked on */ 123#define PLL_CON0_M __BITS(16,25) /* PLL M divide value */ 124#define PLL_CON0_P __BITS( 8,13) /* PLL P divide value */ 125#define PLL_CON0_S __BITS( 0, 2) /* PLL S divide value */ 126 127#define PLL_PMS2FREQ(F, M, P, S) \ 128 ((P) == 0 ? 0 : (((M)*(F))/((P)*(1<<(S))))) 129#define PLL_FREQ(f, v) PLL_PMS2FREQ( \ 130 (f),\ 131 __SHIFTOUT((v), PLL_CON0_M),\ 132 __SHIFTOUT((v), PLL_CON0_P),\ 133 __SHIFTOUT((v), PLL_CON0_S)) 134 135 136/* Watchdog register definitions */ 137#define EXYNOS_WDT_WTCON 0x0000 138#define WTCON_PRESCALER __BITS(15,8) 139#define WTCON_ENABLE __BIT(5) 140#define WTCON_CLOCK_SELECT __BITS(4,3) 141#define WTCON_CLOCK_SELECT_16 __SHIFTIN(0, WTCON_CLOCK_SELECT) 142#define WTCON_CLOCK_SELECT_32 __SHIFTIN(1, WTCON_CLOCK_SELECT) 143#define WTCON_CLOCK_SELECT_64 __SHIFTIN(2, WTCON_CLOCK_SELECT) 144#define WTCON_CLOCK_SELECT_128 __SHIFTIN(3, WTCON_CLOCK_SELECT) 145#define WTCON_INT_ENABLE __BIT(2) 146#define WTCON_RESET_ENABLE __BIT(0) 147#define EXYNOS_WDT_WTDAT 0x0004 148#define WTDAT_RELOAD __BITS(15,0) 149#define EXYNOS_WDT_WTCNT 0x0008 150#define WTCNT_COUNT __BITS(15,0) 151#define EXYNOS_WDT_WTCLRINT 0x000C 152 153 154/* GPIO register definitions */ 155#define EXYNOS_GPIO_GRP_SIZE 0x20 156#define EXYNOS_GPIO_CON 0x00 157#define EXYNOS_GPIO_DAT 0x04 158#define EXYNOS_GPIO_PUD 0x08 159#define EXYNOS_GPIO_DRV 0x0C 160#define EXYNOS_GPIO_CONPWD 0x10 161#define EXYNOS_GPIO_PUDPWD 0x14 162/* rest of space is not used */ 163 164#define EXYNOS_GPIO_FUNC_INPUT 0x0 165#define EXYNOS_GPIO_FUNC_OUTPUT 0x1 166/* intermediate values are devices, definitions dependent on pin */ 167#define EXYNOS_GPIO_FUNC_EXTINT 0xF 168 169#define EXYNOS_GPIO_PIN_FLOAT 0 170#define EXYNOS_GPIO_PIN_PULL_DOWN 1 171#define EXYNOS_GPIO_PIN_PULL_UP 3 172 173 174/* used PMU registers */ 175/* Exynos 4210 or Exynos 5 */ 176#define EXYNOS_PMU_USBDEV_PHY_CTRL 0x704 177#define EXYNOS_PMU_USBHOST_PHY_CTRL 0x708 178/* Exynos 4x12 */ 179#define EXYNOS_PMU_USB_PHY_CTRL 0x704 180#define EXYNOS_PMU_USB_HSIC_1_PHY_CTRL 0x708 181#define EXYNOS_PMU_USB_HSIC_2_PHY_CTRL 0x70C 182 183#define PMU_PHY_ENABLE (1 << 0) 184#define PMU_PHY_DISABLE (0) 185 186#define EXYNOS_PMU_DEBUG_CLKOUT 0x0A00 187 188/* used SYSREG registers */ 189#define EXYNOS5_SYSREG_USB20_PHY_TYPE 0x230 190#define USB20_PHY_HOST_LINK_EN (1 << 0) 191 192 193/* Generic USB registers/constants */ 194#define FSEL_CLKSEL_50M 7 195#define FSEL_CLKSEL_24M 5 196#define FSEL_CLKSEL_20M 4 197#define FSEL_CLKSEL_19200K 3 198#define FSEL_CLKSEL_12M 2 199#define FSEL_CLKSEL_10M 1 200#define FSEL_CLKSEL_9600K 0 201 202#endif /* _ARM_SAMSUNG_EXYNOS_REG_H_ */ 203