rk_gmac.c revision 1.8
1/* $NetBSD: rk_gmac.c,v 1.8 2018/08/12 16:48:05 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30 31__KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.8 2018/08/12 16:48:05 jmcneill Exp $"); 32 33#include <sys/param.h> 34#include <sys/bus.h> 35#include <sys/device.h> 36#include <sys/intr.h> 37#include <sys/systm.h> 38#include <sys/gpio.h> 39 40#include <net/if.h> 41#include <net/if_ether.h> 42#include <net/if_media.h> 43 44#include <dev/mii/miivar.h> 45 46#include <dev/ic/dwc_gmac_var.h> 47#include <dev/ic/dwc_gmac_reg.h> 48 49#include <dev/fdt/fdtvar.h> 50#include <dev/fdt/syscon.h> 51 52#define RK_GMAC_TXDLY_DEFAULT 0x30 53#define RK_GMAC_RXDLY_DEFAULT 0x10 54 55enum rk_gmac_type { 56 GMAC_RK3328 = 1, 57 GMAC_RK3399 58}; 59 60static const struct of_compat_data compat_data[] = { 61 { "rockchip,rk3328-gmac", GMAC_RK3328 }, 62 { "rockchip,rk3399-gmac", GMAC_RK3399 }, 63 { NULL } 64}; 65 66struct rk_gmac_softc { 67 struct dwc_gmac_softc sc_base; 68 struct syscon *sc_syscon; 69 enum rk_gmac_type sc_type; 70}; 71 72/* 73 * RK3328 specific 74 */ 75 76#define RK3328_GRF_MAC_CON0 0x0900 77#define RK3328_GRF_MAC_CON0_RXDLY __BITS(13,7) 78#define RK3328_GRF_MAC_CON0_TXDLY __BITS(6,0) 79 80#define RK3328_GRF_MAC_CON1 0x0904 81#define RK3328_GRF_MAC_CON1_CLKSEL __BITS(12,11) 82#define RK3328_GRF_MAC_CON1_CLKSEL_125M 0 83#define RK3328_GRF_MAC_CON1_CLKSEL_2_5M 2 84#define RK3328_GRF_MAC_CON1_CLKSEL_25M 3 85#define RK3328_GRF_MAC_CON1_MODE __BIT(9) 86#define RK3328_GRF_MAC_CON1_SEL __BITS(6,4) 87#define RK3328_GRF_MAC_CON1_SEL_RGMII 1 88#define RK3328_GRF_MAC_CON1_RXDLY_EN __BIT(1) 89#define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0) 90 91static void 92rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay) 93{ 94 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 95 uint32_t write_mask, write_val; 96 97 syscon_lock(rk_sc->sc_syscon); 98 99 write_mask = (RK3328_GRF_MAC_CON1_MODE | RK3328_GRF_MAC_CON1_SEL) << 16; 100 write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII, RK3328_GRF_MAC_CON1_SEL); 101 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, write_mask | write_val); 102 103#if notyet 104 write_mask = (RK3328_GRF_MAC_CON0_TXDLY | RK3328_GRF_MAC_CON0_RXDLY) << 16; 105 write_val = __SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) | 106 __SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY); 107 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON0, write_mask | write_val); 108 109 write_mask = (RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN) << 16; 110 write_val = RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN; 111 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, write_mask | write_val); 112#endif 113 114 syscon_unlock(rk_sc->sc_syscon); 115} 116 117static void 118rk3328_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 119{ 120 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 121#if 0 122 u_int clksel; 123 124 switch (speed) { 125 case IFM_10_T: 126 clksel = RK3328_GRF_MAC_CON1_CLKSEL_2_5M; 127 break; 128 case IFM_100_TX: 129 clksel = RK3328_GRF_MAC_CON1_CLKSEL_25M; 130 break; 131 default: 132 clksel = RK3328_GRF_MAC_CON1_CLKSEL_125M; 133 break; 134 } 135#endif 136 137 syscon_lock(rk_sc->sc_syscon); 138 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 139 (RK3328_GRF_MAC_CON1_CLKSEL << 16) | 140 __SHIFTIN(RK3328_GRF_MAC_CON1_CLKSEL_125M, RK3328_GRF_MAC_CON1_CLKSEL)); 141 syscon_unlock(rk_sc->sc_syscon); 142} 143 144/* 145 * RK3399 specific 146 */ 147 148#define RK3399_GRF_SOC_CON5 0x0c214 149#define RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL __BITS(11,9) 150#define RK3399_GRF_SOC_CON5_GMAC_FLOWCTRL __BIT(8) 151#define RK3399_GRF_SOC_CON5_GMAC_SPEED __BIT(7) 152#define RK3399_GRF_SOC_CON5_RMII_MODE __BIT(6) 153#define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL __BITS(5,4) 154#define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_125M 0 155#define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_25M 1 156#define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_2_5M 2 157#define RK3399_GRF_SOC_CON5_RMII_CLK_SEL __BIT(3) 158#define RK3399_GRF_SOC_CON6 0x0c218 159#define RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA __BIT(15) 160#define RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG __BITS(14,8) 161#define RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA __BIT(7) 162#define RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG __BITS(6,0) 163 164static void 165rk3399_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay) 166{ 167 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 168 169 const uint32_t con5_mask = 170 (RK3399_GRF_SOC_CON5_RMII_MODE | RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL) << 16; 171 const uint32_t con5 = __SHIFTIN(1, RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL); 172 173 const uint32_t con6_mask = 174 (RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG | RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG) << 16; 175 const uint32_t con6 = 176 __SHIFTIN(rx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG) | 177 __SHIFTIN(tx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG); 178 179 syscon_lock(rk_sc->sc_syscon); 180 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, con5 | con5_mask); 181 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON6, con6 | con6_mask); 182 syscon_unlock(rk_sc->sc_syscon); 183} 184 185static void 186rk3399_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 187{ 188 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 189 u_int clksel; 190 191 switch (speed) { 192 case IFM_10_T: 193 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_2_5M; 194 break; 195 case IFM_100_TX: 196 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_25M; 197 break; 198 default: 199 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_125M; 200 break; 201 } 202 203 const uint32_t con5_mask = 204 RK3399_GRF_SOC_CON5_GMAC_CLK_SEL << 16; 205 const uint32_t con5 = 206 __SHIFTIN(clksel, RK3399_GRF_SOC_CON5_GMAC_CLK_SEL); 207 208 syscon_lock(rk_sc->sc_syscon); 209 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, con5 | con5_mask); 210 syscon_unlock(rk_sc->sc_syscon); 211} 212 213static int 214rk_gmac_reset(const int phandle) 215{ 216 struct fdtbus_gpio_pin *pin_reset; 217 const u_int *reset_delay_us; 218 bool reset_active_low; 219 int len; 220 221 if (!of_hasprop(phandle, "snps,reset-gpio")) 222 return 0; 223 224 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 225 if (pin_reset == NULL) 226 return ENOENT; 227 228 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 229 if (reset_delay_us == NULL || len != 12) 230 return ENXIO; 231 232 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 233 234 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 235 delay(be32toh(reset_delay_us[0])); 236 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 0 : 1); 237 delay(be32toh(reset_delay_us[1])); 238 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 239 delay(be32toh(reset_delay_us[2])); 240 241 return 0; 242} 243 244static int 245rk_gmac_intr(void *arg) 246{ 247 return dwc_gmac_intr(arg); 248} 249 250static int 251rk_gmac_setup_clocks(int phandle) 252{ 253 static const char * const clknames[] = { 254#if 0 255 "stmmaceth", 256 "mac_clk_rx", 257 "mac_clk_tx", 258 "clk_mac_ref", 259 "clk_mac_refout", 260 "aclk_mac", 261 "pclk_mac" 262#else 263 "stmmaceth", 264 "aclk_mac", 265 "pclk_mac", 266 "mac_clk_tx", 267 "mac_clk_rx" 268#endif 269 }; 270 static const char * const rstnames[] = { 271 "stmmaceth" 272 }; 273 struct fdtbus_reset *rst; 274 struct clk *clk; 275 int error, n; 276 277 fdtbus_clock_assign(phandle); 278 279 for (n = 0; n < __arraycount(clknames); n++) { 280 clk = fdtbus_clock_get(phandle, clknames[n]); 281 if (clk == NULL) { 282 aprint_error(": couldn't get %s clock\n", clknames[n]); 283 return ENXIO; 284 } 285 error = clk_enable(clk); 286 if (error != 0) { 287 aprint_error(": couldn't enable %s clock: %d\n", 288 clknames[n], error); 289 return error; 290 } 291 } 292 293 for (n = 0; n < __arraycount(rstnames); n++) { 294 rst = fdtbus_reset_get(phandle, rstnames[n]); 295 if (rst == NULL) { 296 aprint_error(": couldn't get %s reset\n", rstnames[n]); 297 return ENXIO; 298 } 299 error = fdtbus_reset_deassert(rst); 300 if (error != 0) { 301 aprint_error(": couldn't de-assert %s reset: %d\n", 302 rstnames[n], error); 303 return error; 304 } 305 } 306 307 delay(5000); 308 309 return 0; 310} 311 312static int 313rk_gmac_match(device_t parent, cfdata_t cf, void *aux) 314{ 315 struct fdt_attach_args * const faa = aux; 316 317 return of_match_compat_data(faa->faa_phandle, compat_data); 318} 319 320static void 321rk_gmac_attach(device_t parent, device_t self, void *aux) 322{ 323 struct rk_gmac_softc * const rk_sc = device_private(self); 324 struct dwc_gmac_softc * const sc = &rk_sc->sc_base; 325 struct fdt_attach_args * const faa = aux; 326 const int phandle = faa->faa_phandle; 327 const char *phy_mode; 328 char intrstr[128]; 329 bus_addr_t addr; 330 bus_size_t size; 331 u_int tx_delay, rx_delay; 332 333 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 334 aprint_error(": couldn't get registers\n"); 335 return; 336 } 337 338 rk_sc->sc_type = of_search_compatible(phandle, compat_data)->data; 339 340 rk_sc->sc_syscon = fdtbus_syscon_acquire(phandle, "rockchip,grf"); 341 if (rk_sc->sc_syscon == NULL) { 342 aprint_error(": couldn't get grf syscon\n"); 343 return; 344 } 345 346 if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0) 347 tx_delay = RK_GMAC_TXDLY_DEFAULT; 348 349 if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0) 350 rx_delay = RK_GMAC_RXDLY_DEFAULT; 351 352 sc->sc_dev = self; 353 sc->sc_bst = faa->faa_bst; 354 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 355 aprint_error(": couldn't map registers\n"); 356 return; 357 } 358 sc->sc_dmat = faa->faa_dmat; 359 360 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 361 aprint_error(": failed to decode interrupt\n"); 362 return; 363 } 364 365 if (rk_gmac_setup_clocks(phandle) != 0) 366 return; 367 368 if (rk_gmac_reset(phandle) != 0) 369 aprint_error_dev(self, "PHY reset failed\n"); 370 371 /* Rock64 seems to need more time for the reset to complete */ 372 delay(100000); 373 374#if notyet 375 if (of_hasprop(phandle, "snps,force_thresh_dma_mode")) 376 sc->sc_flags |= DWC_GMAC_FORCE_THRESH_DMA_MODE; 377#endif 378 379 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 380 if (phy_mode == NULL) { 381 aprint_error(": missing 'phy-mode' property\n"); 382 return; 383 } 384 385 switch (rk_sc->sc_type) { 386 case GMAC_RK3328: 387 if (strcmp(phy_mode, "rgmii") == 0) { 388 rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay); 389 390 sc->sc_set_speed = rk3328_gmac_set_speed_rgmii; 391 } else { 392 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 393 return; 394 } 395 break; 396 case GMAC_RK3399: 397 if (strcmp(phy_mode, "rgmii") == 0) { 398 rk3399_gmac_set_mode_rgmii(sc, tx_delay, rx_delay); 399 400 sc->sc_set_speed = rk3399_gmac_set_speed_rgmii; 401 } else { 402 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 403 return; 404 } 405 break; 406 } 407 408 aprint_naive("\n"); 409 aprint_normal(": GMAC\n"); 410 411 if (dwc_gmac_attach(sc, GMAC_MII_CLK_150_250M_DIV102) != 0) 412 return; 413 414 if (fdtbus_intr_establish(phandle, 0, IPL_NET, 0, rk_gmac_intr, sc) == NULL) { 415 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 416 return; 417 } 418 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 419} 420 421CFATTACH_DECL_NEW(rk_gmac, sizeof(struct rk_gmac_softc), 422 rk_gmac_match, rk_gmac_attach, NULL, NULL); 423