1/* $NetBSD: rk3288_cru.c,v 1.5 2021/11/13 11:46:32 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2021 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30 31__KERNEL_RCSID(1, "$NetBSD: rk3288_cru.c,v 1.5 2021/11/13 11:46:32 jmcneill Exp $"); 32 33#include <sys/param.h> 34#include <sys/bus.h> 35#include <sys/device.h> 36#include <sys/systm.h> 37 38#include <dev/fdt/fdtvar.h> 39 40#include <arm/rockchip/rk_cru.h> 41#include <arm/rockchip/rk3288_cru.h> 42 43#define PLL_CON(n) (0x0000 + (n) * 4) 44#define MODE_CON 0x0050 45#define CLKSEL_CON(n) (0x0060 + (n) * 4) 46#define CLKGATE_CON(n) (0x0160 + (n) * 4) 47#define SOFTRST_CON(n) (0x01b8 + (n) * 4) 48 49#define GRF_SOC_CON4 0x0410 50#define GRF_MAC_CON1 0x0904 51 52static int rk3288_cru_match(device_t, cfdata_t, void *); 53static void rk3288_cru_attach(device_t, device_t, void *); 54 55static const struct device_compatible_entry compat_data[] = { 56 { .compat = "rockchip,rk3288-cru" }, 57 DEVICE_COMPAT_EOL 58}; 59 60CFATTACH_DECL_NEW(rk3288_cru, sizeof(struct rk_cru_softc), 61 rk3288_cru_match, rk3288_cru_attach, NULL, NULL); 62 63static const char * pll_parents[] = { "xin24m" }; 64static const char * aclk_cpu_src_parents[] = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; 65static const char * uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 66static const char * uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 67static const char * uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 68static const char * uart3_parents[] = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 69static const char * uart4_parents[] = { "clk_uart4_div", "clk_uart4_frac", "xin24m" }; 70static const char * mmc_parents[] = { "cpll", "gpll", "xin24m", "xin24m" }; 71static const char * mac_parents[] = { "mac_pll_src", "ext_gmac" }; 72static const char * mux_2plls_parents[] = { "cpll", "gpll" }; 73static const char * mux_npll_cpll_gpll_parents[] = { "npll", "cpll", "gpll" }; 74static const char * mux_3plls_usb_parents[] = { "cpll", "gpll", "usbphy480m_src", "npll" }; 75 76static struct rk_cru_pll_rate rk3288_pll_rates[] = { 77 /* TODO */ 78}; 79 80static struct rk_cru_clk rk3288_cru_clks[] = { 81 RK3288_PLL(RK3288_PLL_CPLL, "cpll", pll_parents, 82 PLL_CON(8), /* con_base */ 83 MODE_CON, /* mode_reg */ 84 __BIT(8), /* mode_mask */ 85 __BIT(2), /* lock_mask */ 86 rk3288_pll_rates), 87 RK3288_PLL(RK3288_PLL_GPLL, "gpll", pll_parents, 88 PLL_CON(12), /* con_base */ 89 MODE_CON, /* mode_reg */ 90 __BIT(12), /* mode_mask */ 91 __BIT(3), /* lock_mask */ 92 rk3288_pll_rates), 93 RK3288_PLL(RK3288_PLL_NPLL, "npll", pll_parents, 94 PLL_CON(16), /* con_base */ 95 MODE_CON, /* mode_reg */ 96 __BIT(14), /* mode_mask */ 97 __BIT(4), /* lock_mask */ 98 rk3288_pll_rates), 99 100 RK_COMPOSITE_NOGATE(0, "aclk_cpu_src", aclk_cpu_src_parents, 101 CLKSEL_CON(1), /* muxdiv_reg */ 102 __BIT(15), /* mux_mask */ 103 __BITS(7,3), /* div_mask */ 104 0), 105 RK_COMPOSITE_NOMUX(RK3288_ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 106 CLKSEL_CON(1), /* div_reg */ 107 __BITS(9,8), /* div_mask */ 108 CLKGATE_CON(0), /* gate_reg */ 109 __BIT(4), /* gate_mask */ 110 0), 111 RK_COMPOSITE_NOMUX(RK3288_PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 112 CLKSEL_CON(1), /* div_reg */ 113 __BITS(14,12), /* div_mask */ 114 CLKGATE_CON(0), /* gate_reg */ 115 __BIT(5), /* gate_mask */ 116 0), 117 RK_COMPOSITE_NOMUX(RK3288_HCLK_PERI, "hclk_peri", "aclk_peri_src", 118 CLKSEL_CON(10), /* div_reg */ 119 __BITS(9,8), /* div_mask */ 120 CLKGATE_CON(2), /* gate_reg */ 121 __BIT(2), /* gate_mask */ 122 RK_COMPOSITE_POW2), 123 RK_COMPOSITE(0, "aclk_peri_src", mux_2plls_parents, 124 CLKSEL_CON(10), /* muxdiv_reg */ 125 __BIT(15), /* mux_mask */ 126 __BITS(4,0), /* div_mask */ 127 CLKGATE_CON(2), /* gate_reg */ 128 __BIT(0), /* gate_mask */ 129 0), 130 RK_COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", 131 CLKSEL_CON(33), /* div_reg */ 132 __BITS(4,0), /* div_mask */ 133 CLKGATE_CON(5), /* gate_reg */ 134 __BIT(8), /* gate_mask */ 135 0), 136 RK_COMPOSITE_NOMUX(RK3288_PCLK_PERI, "pclk_peri", "aclk_peri_src", 137 CLKSEL_CON(10), /* div_reg */ 138 __BITS(13,12), /* div_mask */ 139 CLKGATE_CON(2), /* gate_reg */ 140 __BIT(3), /* gate_mask */ 141 0), 142 143 /* UARTs */ 144 RK_COMPOSITE(0, "clk_uart0_div", mux_3plls_usb_parents, 145 CLKSEL_CON(13), /* muxdiv_reg */ 146 __BITS(14,13), /* mux_mask */ 147 __BITS(6,0), /* div_mask */ 148 CLKGATE_CON(1), /* gate_reg */ 149 __BIT(8), /* gate_mask */ 150 0), 151 /* XXX TODO: CRU_CLKGATE1_CON bit 9 (clk_uart0_frac_src_gate_en) */ 152 RK_COMPOSITE_FRAC(0, "clk_uart0_frac", "clk_uart0_div", 153 CLKSEL_CON(17), /* fracdiv_reg */ 154 0), 155 RK_COMPOSITE_NOMUX(0, "clk_uart1_div", "uart_src", 156 CLKSEL_CON(14), /* div_reg */ 157 __BITS(6,0), /* div_mask */ 158 CLKGATE_CON(1), /* gate_reg */ 159 __BIT(10), /* gate_mask */ 160 0), 161 /* XXX TODO: CRU_CLKGATE1_CON bit 11 (clk_uart1_frac_src_gate_en) */ 162 RK_COMPOSITE_FRAC(0, "clk_uart1_frac", "clk_uart1_div", 163 CLKSEL_CON(18), /* fracdiv_reg */ 164 0), 165 RK_COMPOSITE_NOMUX(0, "clk_uart2_div", "uart_src", 166 CLKSEL_CON(15), /* div_reg */ 167 __BITS(6,0), /* div_mask */ 168 CLKGATE_CON(1), /* gate_reg */ 169 __BIT(12), /* gate_mask */ 170 0), 171 /* XXX TODO: CRU_CLKGATE1_CON bit 13 (clk_uart2_frac_src_gate_en) */ 172 RK_COMPOSITE_FRAC(0, "clk_uart2_frac", "clk_uart2_div", 173 CLKSEL_CON(19), /* fracdiv_reg */ 174 0), 175 RK_COMPOSITE_NOMUX(0, "clk_uart3_div", "uart_src", 176 CLKSEL_CON(16), /* div_reg */ 177 __BITS(6,0), /* div_mask */ 178 CLKGATE_CON(1), /* gate_reg */ 179 __BIT(14), /* gate_mask */ 180 0), 181 /* XXX TODO: CRU_CLKGATE1_CON bit 15 (clk_uart3_frac_src_gate_en) */ 182 RK_COMPOSITE_FRAC(0, "clk_uart3_frac", "clk_uart3_div", 183 CLKSEL_CON(20), /* fracdiv_reg */ 184 0), 185 RK_COMPOSITE_NOMUX(0, "clk_uart4_div", "uart_src", 186 CLKSEL_CON(3), /* div_reg */ 187 __BITS(6,0), /* div_mask */ 188 CLKGATE_CON(2), /* gate_reg */ 189 __BIT(12), /* gate_mask */ 190 0), 191 /* XXX TODO: CRU_CLKGATE2_CON bit 13 (clk_uart4_frac_src_gate_en) */ 192 RK_COMPOSITE_FRAC(0, "clk_uart4_frac", "clk_uart4_div", 193 CLKSEL_CON(7), /* fracdiv_reg */ 194 0), 195 196 /* SD/eMMC/SDIO */ 197 RK_COMPOSITE(RK3288_SCLK_SDMMC, "sclk_sdmmc", mmc_parents, 198 CLKSEL_CON(11), /* muxdiv_reg */ 199 __BITS(7,6), /* mux_mask */ 200 __BITS(5,0), /* div_mask */ 201 CLKGATE_CON(13), /* gate_reg */ 202 __BIT(0), /* gate_mask */ 203 0), 204 RK_COMPOSITE(RK3288_SCLK_SDIO0, "sclk_sdio0", mmc_parents, 205 CLKSEL_CON(12), /* muxdiv_reg */ 206 __BITS(7,6), /* mux_mask */ 207 __BITS(5,0), /* div_mask */ 208 CLKGATE_CON(13), /* gate_reg */ 209 __BIT(1), /* gate_mask */ 210 0), 211 RK_COMPOSITE(RK3288_SCLK_SDIO1, "sclk_sdio1", mmc_parents, 212 CLKSEL_CON(34), /* muxdiv_reg */ 213 __BITS(15,14), /* mux_mask */ 214 __BITS(13,8), /* div_mask */ 215 CLKGATE_CON(13), /* gate_reg */ 216 __BIT(2), /* gate_mask */ 217 0), 218 RK_COMPOSITE(RK3288_SCLK_EMMC, "sclk_emmc", mmc_parents, 219 CLKSEL_CON(12), /* muxdiv_reg */ 220 __BITS(15,14), /* mux_mask */ 221 __BITS(13,8), /* div_mask */ 222 CLKGATE_CON(13), /* gate_reg */ 223 __BIT(3), /* gate_mask */ 224 0), 225 226 /* MAC */ 227 RK_COMPOSITE(0, "mac_pll_src", mux_npll_cpll_gpll_parents, 228 CLKSEL_CON(21), /* muxdiv_reg */ 229 __BITS(1,0), /* mux_mask */ 230 __BITS(12,8), /* div_mask */ 231 CLKGATE_CON(2), /* gate_reg */ 232 __BIT(5), /* gate_mask */ 233 0), 234 235 /* Crypto */ 236 RK_COMPOSITE_NOMUX(RK3288_SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 237 CLKSEL_CON(26), /* div_reg */ 238 __BITS(7,6), /* div_mask */ 239 CLKGATE_CON(5), /* gate_reg */ 240 __BIT(4), /* gate_mask */ 241 0), 242 243 /* SPI */ 244 RK_COMPOSITE(RK3288_SCLK_SPI0, "sclk_spi0", mux_2plls_parents, 245 CLKSEL_CON(25), /* muxdiv_reg */ 246 __BIT(7), /* mux_mask */ 247 __BITS(6,0), /* div_mask */ 248 CLKGATE_CON(2), /* gate_reg */ 249 __BIT(9), /* gate_mask */ 250 0), 251 RK_COMPOSITE(RK3288_SCLK_SPI1, "sclk_spi1", mux_2plls_parents, 252 CLKSEL_CON(25), /* muxdiv_reg */ 253 __BIT(15), /* mux_mask */ 254 __BITS(14,8), /* div_mask */ 255 CLKGATE_CON(2), /* gate_reg */ 256 __BIT(10), /* gate_mask */ 257 0), 258 RK_COMPOSITE(RK3288_SCLK_SPI2, "sclk_spi2", mux_2plls_parents, 259 CLKSEL_CON(39), /* muxdiv_reg */ 260 __BIT(7), /* mux_mask */ 261 __BITS(6,0), /* div_mask */ 262 CLKGATE_CON(2), /* gate_reg */ 263 __BIT(11), /* gate_mask */ 264 0), 265 266 /* TSADC */ 267 RK_COMPOSITE_NOMUX(RK3288_SCLK_TSADC, "sclk_tsadc", "xin32k", 268 CLKSEL_CON(2), /* div_reg */ 269 __BITS(5,0), /* div_mask */ 270 CLKGATE_CON(2), /* gate_reg */ 271 __BIT(7), /* gate_mask */ 272 0), 273 274 RK_DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLKSEL_CON(1), __BITS(2,0), 0), 275 RK_DIV(0, "clk_24m", "xin24m", CLKSEL_CON(2), __BITS(12,8), 0), 276 RK_DIV(0, "pclk_pd_alive", "gpll", CLKSEL_CON(33), __BITS(12,8), 0), 277 278 RK_MUX(RK3288_SCLK_UART0, "sclk_uart0", uart0_parents, CLKSEL_CON(13), __BITS(9,8)), 279 RK_MUX(RK3288_SCLK_UART1, "sclk_uart1", uart1_parents, CLKSEL_CON(14), __BITS(9,8)), 280 RK_MUX(RK3288_SCLK_UART2, "sclk_uart2", uart2_parents, CLKSEL_CON(15), __BITS(9,8)), 281 RK_MUX(RK3288_SCLK_UART3, "sclk_uart3", uart3_parents, CLKSEL_CON(16), __BITS(9,8)), 282 RK_MUX(RK3288_SCLK_UART4, "sclk_uart4", uart4_parents, CLKSEL_CON(3), __BITS(9,8)), 283 RK_MUX(0, "uart_src", mux_2plls_parents, CLKSEL_CON(15), __BIT(15)), 284 RK_MUX(RK3288_SCLK_MAC, "mac_clk", mac_parents, CLKSEL_CON(21), __BIT(4)), 285 286 RK_GATE(RK3288_ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLKGATE_CON(0), 3), 287 RK_GATE(0, "gpll_aclk_cpu", "gpll", CLKGATE_CON(0), 10), 288 RK_GATE(0, "cpll_aclk_cpu", "cpll", CLKGATE_CON(0), 11), 289 RK_GATE(RK3288_ACLK_PERI, "aclk_peri", "aclk_peri_src", CLKGATE_CON(2), 1), 290 RK_GATE(RK3288_SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", CLKGATE_CON(5), 0), 291 RK_GATE(RK3288_SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", CLKGATE_CON(5), 1), 292 RK_GATE(RK3288_SCLK_MACREF, "sclk_macref", "mac_clk", CLKGATE_CON(5), 2), 293 RK_GATE(RK3288_SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", CLKGATE_CON(5), 3), 294 RK_GATE(RK3288_PCLK_SPI0, "pclk_spi0", "pclk_peri", CLKGATE_CON(6), 4), 295 RK_GATE(RK3288_PCLK_SPI1, "pclk_spi1", "pclk_peri", CLKGATE_CON(6), 5), 296 RK_GATE(RK3288_PCLK_SPI2, "pclk_spi2", "pclk_peri", CLKGATE_CON(6), 6), 297 RK_GATE(RK3288_PCLK_I2C1, "pclk_i2c1", "pclk_peri", CLKGATE_CON(6), 13), 298 RK_GATE(RK3288_PCLK_I2C3, "pclk_i2c3", "pclk_peri", CLKGATE_CON(6), 14), 299 RK_GATE(RK3288_PCLK_I2C4, "pclk_i2c4", "pclk_peri", CLKGATE_CON(6), 15), 300 RK_GATE(RK3288_PCLK_I2C5, "pclk_i2c5", "pclk_peri", CLKGATE_CON(7), 0), 301 RK_GATE(RK3288_PCLK_TSADC, "pclk_tsadc", "pclk_peri", CLKGATE_CON(7), 2), 302 RK_GATE(RK3288_HCLK_USBHOST0, "hclk_host0", "hclk_peri", CLKGATE_CON(7), 6), 303 RK_GATE(RK3288_HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLKGATE_CON(7), 7), 304 RK_GATE(RK3288_HCLK_HSIC, "hclk_hsic", "hclk_peri", CLKGATE_CON(7), 8), 305 RK_GATE(RK3288_PCLK_GMAC, "pclk_gmac", "pclk_peri", CLKGATE_CON(8), 1), 306 RK_GATE(RK3288_HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", CLKGATE_CON(8), 3), 307 RK_GATE(RK3288_HCLK_SDIO0, "hclk_sdio0", "hclk_peri", CLKGATE_CON(8), 4), 308 RK_GATE(RK3288_HCLK_SDIO1, "hclk_sdio1", "hclk_peri", CLKGATE_CON(8), 5), 309 RK_GATE(RK3288_ACLK_GMAC, "aclk_gmac", "aclk_peri", CLKGATE_CON(8), 0), 310 RK_GATE(RK3288_HCLK_EMMC, "hclk_emmc", "hclk_peri", CLKGATE_CON(8), 6), 311 RK_GATE(RK3288_PCLK_I2C0, "pclk_i2c0", "pclk_cpu", CLKGATE_CON(10), 2), 312 RK_GATE(RK3288_PCLK_I2C2, "pclk_i2c2", "pclk_cpu", CLKGATE_CON(10), 3), 313 RK_GATE(RK3288_ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", CLKGATE_CON(10), 12), 314 RK_GATE(RK3288_ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", CLKGATE_CON(11), 6), 315 RK_GATE(RK3288_HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", CLKGATE_CON(11), 7), 316 RK_GATE(RK3288_PCLK_UART2, "pclk_uart2", "pclk_cpu", CLKGATE_CON(11), 9), 317 RK_GATE(RK3288_PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLKGATE_CON(11), 11), 318 RK_GATE(RK3288_SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLKGATE_CON(13), 4), 319 RK_GATE(RK3288_SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLKGATE_CON(13), 5), 320 RK_GATE(RK3288_SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLKGATE_CON(13), 6), 321 RK_GATE(RK3288_PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", CLKGATE_CON(14), 1), 322 RK_GATE(RK3288_PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", CLKGATE_CON(14), 2), 323 RK_GATE(RK3288_PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", CLKGATE_CON(14), 3), 324 RK_GATE(RK3288_PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", CLKGATE_CON(14), 4), 325 RK_GATE(RK3288_PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", CLKGATE_CON(14), 5), 326 RK_GATE(RK3288_PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", CLKGATE_CON(14), 6), 327 RK_GATE(RK3288_PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", CLKGATE_CON(14), 7), 328 RK_GATE(RK3288_PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", CLKGATE_CON(14), 8), 329 RK_GATE(RK3288_PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", CLKGATE_CON(17), 4), 330 RK_SECURE_GATE(RK3288_PCLK_WDT, "pclk_wdt", "pclk_pd_alive"), 331}; 332 333static int 334rk3288_cru_match(device_t parent, cfdata_t cf, void *aux) 335{ 336 struct fdt_attach_args * const faa = aux; 337 338 return of_compatible_match(faa->faa_phandle, compat_data); 339} 340 341static void 342rk3288_cru_attach(device_t parent, device_t self, void *aux) 343{ 344 struct rk_cru_softc * const sc = device_private(self); 345 struct fdt_attach_args * const faa = aux; 346 347 sc->sc_dev = self; 348 sc->sc_phandle = faa->faa_phandle; 349 sc->sc_bst = faa->faa_bst; 350 351 sc->sc_clks = rk3288_cru_clks; 352 sc->sc_nclks = __arraycount(rk3288_cru_clks); 353 354 sc->sc_grf_soc_status = 0x0284; 355 sc->sc_softrst_base = SOFTRST_CON(0); 356 357 if (rk_cru_attach(sc) != 0) 358 return; 359 360 aprint_naive("\n"); 361 aprint_normal(": RK3288 CRU\n"); 362 363 rk_cru_print(sc); 364} 365