1/* $NetBSD: amlogic_reg.h,v 1.10 2015/03/22 17:28:22 jmcneill Exp $ */ 2 3/*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#ifndef _ARM_TEGRA_APBREG_H 30#define _ARM_TEGRA_APBREG_H 31 32#define APB_MISC_PP_CONFIG_CTL_0_REG 0x24 33#define APB_MISC_PP_PINMUX_GLOBAL_0_0_REG 0x40 34#define APB_MISC_PP_PULLUPDOWN_REG_C_0_REG 0xa8 35#define APB_MISC_SC1X_PADS_VIP_VCLKCTRL_0_REG 0x428 36#define APB_MISC_GP_HIDREV_0_REG 0x804 37#define APB_MISC_GP_MIPI_PAD_CTRL_0_REG 0x820 38#define APB_MISC_GP_AOCFG1PADCTRL_0_REG 0x868 39#define APB_MISC_GP_AOCFG2PADCTRL_0_REG 0x86c 40#define APB_MISC_GP_ATCFG1PADCTRL_0_REG 0x870 41#define APB_MISC_GP_ATCFG2PADCTRL_0_REG 0x874 42#define APB_MISC_GP_ATCFG3PADCTRL_0_REG 0x878 43#define APB_MISC_GP_ATCFG4PADCTRL_0_REG 0x87c 44#define APB_MISC_GP_ATCFG5PADCTRL_0_REG 0x880 45#define APB_MISC_GP_CDEV1CFGPADCTRL_0_REG 0x884 46#define APB_MISC_GP_CDEV2CFGPADCTRL_0_REG 0x888 47#define APB_MISC_GP_DAP1CFGPADCTRL_0_REG 0x890 48#define APB_MISC_GP_DAP2CFGPADCTRL_0_REG 0x894 49#define APB_MISC_GP_DAP3CFGPADCTRL_0_REG 0x898 50#define APB_MISC_GP_DAP4CFGPADCTRL_0_REG 0x89c 51#define APB_MISC_GP_DBGCFGPADCTRL_0_REG 0x8a0 52#define APB_MISC_GP_SDIO3CFGPADCTRL_0_REG 0x8b0 53#define APB_MISC_GP_SPICFGPADCTRL_0_REG 0x8b4 54#define APB_MISC_GP_UAACFGPADCTRL_0_REG 0x8b8 55#define APB_MISC_GP_UABCFGPADCTRL_0_REG 0x8bc 56#define APB_MISC_GP_UART2CFGPADCTRL_0_REG 0x8c0 57#define APB_MISC_GP_UART3CFGPADCTRL_0_REG 0x8c4 58#define APB_MISC_GP_SDIO1CFGPADCTRL_0_REG 0x8ec 59#define APB_MISC_GP_DDCCFGPADCTRL_0_REG 0x8fc 60#define APB_MISC_GP_GMCAFGPADCTRL_0_REG 0x900 61#define APB_MISC_GP_GMECFGPADCTRL_0_REG 0x910 62#define APB_MISC_GP_GMFCFGPADCTRL_0_REG 0x914 63#define APB_MISC_GP_GMGCFGPADCTRL_0_REG 0x918 64#define APB_MISC_GP_GMHCFGPADCTRL_0_REG 0x91c 65#define APB_MISC_GP_OWRCFGPADCTRL_0_REG 0x920 66#define APB_MISC_GP_UADCFGPADCTRL_0_REG 0x924 67#define APB_MISC_GP_GPVCFGPADCTRL_0_REG 0x928 68#define APB_MISC_GP_DEV3CFGPADCTRL_0_REG 0x92c 69#define APB_MISC_GP_CECCFGPADCTRL_0_REG 0x938 70#define APB_MISC_GP_ATCFG6PADCTRL_0_REG 0x994 71#define APB_MISC_GP_DAP5CFGPADCTRL_0_REG 0x998 72#define APB_MISC_GP_USB_VBUS_EN_CFGPADCTRL_0_REG 0x99c 73#define APB_MISC_GP_AOCFG3PADCTRL_0_REG 0x9a8 74#define APB_MISC_GP_AOCFG0PADCTRL_0_REG 0x9b0 75#define APB_MISC_GP_HVCFG0PADCTRL_0_REG 0x9b4 76#define APB_MISC_GP_SDIO4CFGPADCTRL_0_REG 0x9c4 77#define APB_MISC_GP_AOCFG4PADCTRL_0_REG 0x9c8 78#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0_REG 0xc00 79#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0_REG 0xc04 80#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0_REG 0xc08 81 82#define APB_MISC_GP_HIDREV_0_MINORREV __BITS(19,16) 83#define APB_MISC_GP_HIDREV_0_CHIPID __BITS(15,8) 84#define APB_MISC_GP_HIDREV_0_MAJORREV __BITS(7,4) 85#define APB_MISC_GP_HIDREV_0_HIDFAM __BITS(3,0) 86 87#endif /* _ARM_TEGRA_APBREG_H */ 88