1/******************************************************************************* 2Copyright (C) Marvell International Ltd. and its affiliates 3 4Developed by Semihalf 5 6******************************************************************************** 7Marvell BSD License 8 9If you received this File from Marvell, you may opt to use, redistribute and/or 10modify this File under the following licensing terms. 11Redistribution and use in source and binary forms, with or without modification, 12are permitted provided that the following conditions are met: 13 14 * Redistributions of source code must retain the above copyright notice, 15 this list of conditions and the following disclaimer. 16 17 * Redistributions in binary form must reproduce the above copyright 18 notice, this list of conditions and the following disclaimer in the 19 documentation and/or other materials provided with the distribution. 20 21 * Neither the name of Marvell nor the names of its contributors may be 22 used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 26ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 29ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 32ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 36*******************************************************************************/ 37 38#ifndef _ARMADAXPREG_H_ 39#define _ARMADAXPREG_H_ 40 41#include <arm/marvell/mvsocreg.h> 42#include <evbarm/marvell/marvellvar.h> 43 44#define ARMADAXP_UNITID_DDR MVSOC_UNITID_DDR 45#define ARMADAXP_UNITID_DEVBUS MVSOC_UNITID_DEVBUS 46#define ARMADAXP_UNITID_MLMB MVSOC_UNITID_MLMB 47#define ARMADAXP_UNITID_PEX MVSOC_UNITID_PEX 48#define ARMADAXP_UNITID_USB 0x5 /* USB registers */ 49#define ARMADAXP_UNITID_XORE0 0x6 /* Reserved? */ 50#define ARMADAXP_UNITID_GBE0 0x7 51#define ARMADAXP_UNITID_GBE1 0x7 52#define ARMADAXP_UNITID_GBE2 0x3 53#define ARMADAXP_UNITID_GBE3 0x3 54#define ARMADAXP_UNITID_PEX0 MVSOC_UNITID_PEX 55#define ARMADAXP_UNITID_PEX1 0x8 56#define ARMADAXP_UNITID_PEX2 MVSOC_UNITID_PEX 57#define ARMADAXP_UNITID_PEX3 0x8 58#define ARMADAXP_UNITID_CRYPT 0x9 59#define ARMADAXP_UNITID_SATA 0xa 60#define ARMADAXP_UNITID_BM 0xc 61#define ARMADAXP_UNITID_NAND 0xd /* NAND registers */ 62#define ARMADAXP_UNITID_SDIO 0xd /* SDIO registers */ 63#define ARMADAXP_UNITID_LCD 0xe 64#define ARMADAXP_UNITID_XORE1 0xf 65 66/* DDR Attributes */ 67#define ARMADAXP_ATTR_DDR_CS0 0x0e 68#define ARMADAXP_ATTR_DDR_CS1 0x0d 69#define ARMADAXP_ATTR_DDR_CS2 0x0b 70#define ARMADAXP_ATTR_DDR_CS3 0x07 71 72/* DEVBUS Attributes */ 73#define ARMADAXP_ATTR_DEVBUS_UART 0x01 74#define ARMADAXP_ATTR_DEVBUS_SPI0_CS0 0x1e 75#define ARMADAXP_ATTR_DEVBUS_SPI0_CS1 0x5e 76#define ARMADAXP_ATTR_DEVBUS_SPI0_CS2 0x9e 77#define ARMADAXP_ATTR_DEVBUS_SPI0_CS3 0xde 78#define ARMADAXP_ATTR_DEVBUS_SPI0_CS4 0x1f 79#define ARMADAXP_ATTR_DEVBUS_SPI0_CS5 0x5f 80#define ARMADAXP_ATTR_DEVBUS_SPI0_CS6 0x9f 81#define ARMADAXP_ATTR_DEVBUS_SPI0_CS7 0xdf 82#define ARMADAXP_ATTR_DEVBUS_SPI1_CS0 0x1a 83#define ARMADAXP_ATTR_DEVBUS_SPI1_CS1 0x5a 84#define ARMADAXP_ATTR_DEVBUS_SPI1_CS2 0x9a 85#define ARMADAXP_ATTR_DEVBUS_SPI1_CS3 0xda 86#define ARMADAXP_ATTR_DEVBUS_SPI1_CS4 0x1b 87#define ARMADAXP_ATTR_DEVBUS_SPI1_CS5 0x5b 88#define ARMADAXP_ATTR_DEVBUS_SPI1_CS6 0x9b 89#define ARMADAXP_ATTR_DEVBUS_SPI1_CS7 0xdb 90#define ARMADAXP_ATTR_DEVBUS_DEV_CS0 0x3e 91#define ARMADAXP_ATTR_DEVBUS_DEV_CS1 0x3d 92#define ARMADAXP_ATTR_DEVBUS_DEV_CS2 0x3b 93#define ARMADAXP_ATTR_DEVBUS_DEV_CS3 0x37 94#define ARMADAXP_ATTR_DEVBUS_BOOT_CS 0x2f 95#define ARMADAXP_ATTR_DEVBUS_BOOT_ROM 0x1d 96 97/* NAND Attributes */ 98#define ARMADAXP_ATTR_NAND_RESERVED 0x20 99 100/* PCIe Attributes */ 101/* port 0 has 4 lanes. port 1 has either 4 or 1 lanes. */ 102#define ARMADAXP_ATTR_PEXx0_MEM 0xe8 103#define ARMADAXP_ATTR_PEXx0_IO 0xe0 104#define ARMADAXP_ATTR_PEXx1_MEM 0xd8 105#define ARMADAXP_ATTR_PEXx1_IO 0xd0 106#define ARMADAXP_ATTR_PEXx2_MEM 0xb8 107#define ARMADAXP_ATTR_PEXx2_IO 0xb0 108#define ARMADAXP_ATTR_PEXx3_MEM 0x78 109#define ARMADAXP_ATTR_PEXx3_IO 0x70 110/* port 2, 3 has only 1 lane */ 111#define ARMADAXP_ATTR_PEX2_MEM 0xf8 112#define ARMADAXP_ATTR_PEX2_IO 0xf0 113#define ARMADAXP_ATTR_PEX3_MEM 0xf8 114#define ARMADAXP_ATTR_PEX3_IO 0xf0 115 116/* GbE Attributes */ 117#define ARMADAXP_ATTR_GBE_RESERVED 0x00 118 119/* BM Attributes */ 120#define ARMADAXP_ATTR_BM_RESERVED 0x00 121 122/* CRYPT Attributes */ 123#define ARMADAXP_ATTR_CRYPT_SWAP_MASK __BITS(1,0) 124#define ARMADAXP_ATTR_CRYPT_SWAP_B (0x0 << 0) 125#define ARMADAXP_ATTR_CRYPT_SWAP_NONE (0x1 << 0) 126#define ARMADAXP_ATTR_CRYPT_SWAP_BW (0x2 << 0) 127#define ARMADAXP_ATTR_CRYPT_SWAP_W (0x3 << 0) 128#define ARMADAXP_ATTR_CRYPT_UNIT_MASK __BITS(3,2) 129#define ARMADAXP_ATTR_CRYPT_UNIT0 (0x1 << 2) 130#define ARMADAXP_ATTR_CRYPT_UNIT1 (0x2 << 2) 131 132#define ARMADAXP_ATTR_CRYPT0_NOSWAP \ 133 (ARMADAXP_ATTR_CRYPT_SWAP_NONE|ARMADAXP_ATTR_CRYPT_UNIT0) 134#define ARMADAXP_ATTR_CRYPT0_SWAP_BYTE \ 135 (ARMADAXP_ATTR_CRYPT_SWAP_B|ARMADAXP_ATTR_CRYPT_UNIT0) 136#define ARMADAXP_ATTR_CRYPT0_SWAP_BYTE_WORD \ 137 (ARMADAXP_ATTR_CRYPT_SWAP_BW|ARMADAXP_ATTR_CRYPT_UNIT0) 138#define ARMADAXP_ATTR_CRYPT0_SWAP_WORD \ 139 (ARMADAXP_ATTR_CRYPT_SWAP_W|ARMADAXP_ATTR_CRYPT_UNIT0) 140 141#define ARMADAXP_ATTR_CRYPT1_NOSWAP \ 142 (ARMADAXP_ATTR_CRYPT_SWAP_NONE|ARMADAXP_ATTR_CRYPT_UNIT1) 143#define ARMADAXP_ATTR_CRYPT1_SWAP_BYTE \ 144 (ARMADAXP_ATTR_CRYPT_SWAP_B|ARMADAXP_ATTR_CRYPT_UNIT1) 145#define ARMADAXP_ATTR_CRYPT1_SWAP_BYTE_WORD \ 146 (ARMADAXP_ATTR_CRYPT_SWAP_BW|ARMADAXP_ATTR_CRYPT_UNIT1) 147#define ARMADAXP_ATTR_CRYPT1_SWAP_WORD \ 148 (ARMADAXP_ATTR_CRYPT_SWAP_W|ARMADAXP_ATTR_CRYPT_UNIT1) 149 150 151#define ARMADAXP_IRQ_ERR_SUMMARY 4 152 153#define ARMADAXP_IRQ_GBE0_TH_RXTX 8 /* GBE0_TH_RXTX_Int */ 154#define ARMADAXP_IRQ_GBE1_TH_RXTX 10 /* GBE1_TH_RXTX_Int */ 155#define ARMADAXP_IRQ_GBE2_TH_RXTX 12 /* GBE2_TH_RXTX_Int */ 156#define ARMADAXP_IRQ_GBE3_TH_RXTX 14 /* GBE3_TH_RXTX_Int */ 157 158#define ARMADAXP_IRQ_LCD 29 159#define ARMADAXP_IRQ_SPI 30 160#define ARMADAXP_IRQ_TWSI0 31 161#define ARMADAXP_IRQ_TWSI1 32 162#define ARMADAXP_IRQ_IDMA0 33 /* IDMA Channel 0 */ 163#define ARMADAXP_IRQ_IDMA1 34 /* IDMA Channel 1 */ 164#define ARMADAXP_IRQ_IDMA2 35 /* IDMA Channel 2 */ 165#define ARMADAXP_IRQ_IDMA3 36 /* IDMA Channel 3 */ 166#define ARMADAXP_IRQ_TIMER0 37 167#define ARMADAXP_IRQ_TIMER1 38 168#define ARMADAXP_IRQ_TIMER2 39 169#define ARMADAXP_IRQ_TIMER3 40 170#define ARMADAXP_IRQ_UART0 41 171#define ARMADAXP_IRQ_UART1 42 172#define ARMADAXP_IRQ_UART2 43 173#define ARMADAXP_IRQ_UART3 44 174#if 0 175#define ARMADAXP_IRQ_USB0 45 176#define ARMADAXP_IRQ_USB1 46 177#define ARMADAXP_IRQ_USB2 47 178#else 179/* 180 * According to functional specification (MV-S107021-00B.pdf), interrupt number 181 * for USB0_int is 47, in fact this number is 45. Because of that interrupt 182 * number definitions are not equivalent to ArmadaXP functional specification 183 * (MV-S107021-00B.pdf). 184 */ 185#define ARMADAXP_IRQ_USB0 45 /* USB2 */ 186#define ARMADAXP_IRQ_USB1 46 /* USB1 */ 187#define ARMADAXP_IRQ_USB2 47 /* USB0 */ 188#endif 189#define ARMADAXP_IRQ_CESA0 48 190#define ARMADAXP_IRQ_CESA1 49 191#define ARMADAXP_IRQ_RTC 50 192#define ARMADAXP_IRQ_XOR0CH0 51 /* XOR0 Ch0 */ 193#define ARMADAXP_IRQ_XOR0CH1 52 /* XOR0 Ch1 */ 194#define ARMADAXP_IRQ_BM 53 /* Buffer Management */ 195#define ARMADAXP_IRQ_SDIO 54 196#define ARMADAXP_IRQ_SATA0 55 197#define ARMADAXP_IRQ_TDM 56 198#define ARMADAXP_IRQ_SATA1 57 199#define ARMADAXP_IRQ_PEX00 58 /* PCIe Port0.0 INTA/B/C/D */ 200#define ARMADAXP_IRQ_PEX01 59 /* PCIe Port0.1 INTA/B/C/D */ 201#define ARMADAXP_IRQ_PEX02 60 /* PCIe Port0.2 INTA/B/C/D */ 202#define ARMADAXP_IRQ_PEX03 61 /* PCIe Port0.3 INTA/B/C/D */ 203#define ARMADAXP_IRQ_PEX10 62 /* PCIe Port1.0 INTA/B/C/D */ 204#define ARMADAXP_IRQ_PEX11 63 /* PCIe Port1.1 INTA/B/C/D */ 205#define ARMADAXP_IRQ_PEX12 64 /* PCIe Port1.2 INTA/B/C/D */ 206#define ARMADAXP_IRQ_PEX13 65 /* PCIe Port1.3 INTA/B/C/D */ 207#define ARMADAXP_IRQ_GBE0_SUM 66 208#define ARMADAXP_IRQ_XOR1CH2 94 /* XOR1 Ch2 */ 209#define ARMADAXP_IRQ_XOR1CH3 95 /* XOR1 Ch3 */ 210#define ARMADAXP_IRQ_PEX2 99 /* PCIe Port2 INTA/B/C/D */ 211#define ARMADAXP_IRQ_PEX3 103 /* PCIe Port3 INTA/B/C/D */ 212#define ARMADAXP_IRQ_PMU 107 /* Power Management Unit */ 213 214#define ARMADAXP_IRQ_SOURCES 116 215 216/* 217 * IRQ mappings for Error Interrupt Cause(ARMADAXP_MLMB_MPIC_ERR_CAUSE) 218 */ 219#define ARMADAXP_IRQ_ERROR_BASE 120 220#define ARMADAXP_IRQ_ERROR_SOURCES 32 221#define ARMADAXP_IRQ_ERROR(x) (120 + (x)) 222#define ARMADAXP_IRQ_ERROR_BIT(irq) (1 << irq) 223 224#define ARMADAXP_IRQ_CESA0_ERR ARMADAXP_IRQ_ERROR(0) 225#define ARMADAXP_IRQ_DEVBUS_ERR ARMADAXP_IRQ_ERROR(1) 226#define ARMADAXP_IRQ_IDMA_ERR ARMADAXP_IRQ_ERROR(2) 227#define ARMADAXP_IRQ_XOR1_ERR ARMADAXP_IRQ_ERROR(3) 228#define ARMADAXP_IRQ_PEX0_ERR ARMADAXP_IRQ_ERROR(4) 229#define ARMADAXP_IRQ_PEX1_ERR ARMADAXP_IRQ_ERROR(5) 230#define ARMADAXP_IRQ_GBE_ERR ARMADAXP_IRQ_ERROR(6) 231#define ARMADAXP_IRQ_CESA1_ERR ARMADAXP_IRQ_ERROR(7) 232#define ARMADAXP_IRQ_USB_ERR ARMADAXP_IRQ_ERROR(8) 233#define ARMADAXP_IRQ_DRAM_ERR ARMADAXP_IRQ_ERROR(9) 234#define ARMADAXP_IRQ_XOR0_ERR ARMADAXP_IRQ_ERROR(10) 235#define ARMADAXP_IRQ_BM_ERR ARMADAXP_IRQ_ERROR(12) 236#define ARMADAXP_IRQ_CIB_ERR ARMADAXP_IRQ_ERROR(13) 237#define ARMADAXP_IRQ_PEX2_ERR ARMADAXP_IRQ_ERROR(15) 238#define ARMADAXP_IRQ_PEX3_ERR ARMADAXP_IRQ_ERROR(16) 239#define ARMADAXP_IRQ_SATA0_ERR ARMADAXP_IRQ_ERROR(17) 240#define ARMADAXP_IRQ_SATA1_ERR ARMADAXP_IRQ_ERROR(18) 241#define ARMADAXP_IRQ_TDM_ERR ARMADAXP_IRQ_ERROR(20) 242#define ARMADAXP_IRQ_NAND_ERR ARMADAXP_IRQ_ERROR(21) 243 244#define ARMADAXP_MLMB_NWINDOW 20 245#define ARMADAXP_MLMB_NREMAP 8 246 247/* 248 * Physical address of integrated peripherals 249 */ 250 251#undef UNITID2PHYS 252#define UNITID2PHYS(uid) ((ARMADAXP_UNITID_ ## uid) << 16) 253 254/* 255 * Real-Time Clock Unit Registers 256 */ 257#define ARMADAXP_RTC_BASE (MVSOC_DEVBUS_BASE + 0x0300) 258 259/* 260 * SPI Interface Registers 261 */ 262#define ARMADAXP_SPI_BASE (MVSOC_DEVBUS_BASE + 0x0600) 263 264/* 265 * TWSI Interface Registers 266 */ 267#define ARMADAXP_TWSI1_BASE (MVSOC_DEVBUS_BASE + 0x1100) 268 269/* 270 * UART Interface Registers 271 */ /* NS16550 compatible */ 272#define ARMADAXP_COM2_BASE (MVSOC_DEVBUS_BASE + 0x2200) 273#define ARMADAXP_COM3_BASE (MVSOC_DEVBUS_BASE + 0x2300) 274 275/* 276 * General Purpose Input/Output Port Registers 277 */ 278#define ARMADAXP_GPIO0_BASE (MVSOC_DEVBUS_BASE + 0x8100) 279#define ARMADAXP_GPIO1_BASE (MVSOC_DEVBUS_BASE + 0x8120) 280#define ARMADAXP_GPIO2_BASE (MVSOC_DEVBUS_BASE + 0x8140) 281 282/* 283 * Miscellaneous Register 284 */ 285#define ARMADAXP_MISC_BASE (MVSOC_DEVBUS_BASE + 0x8200) 286 287#define ARMADAXP_MISC_PMCGC 0x20 /* PM Clock Gating Control */ 288#define ARMADAXP_MISC_SAR_LO 0x30 /* Sample At Reset Low */ 289#define ARMADAXP_MISC_SAR_HI 0x34 /* Sample At Reset High */ 290#define ARMADAXP_MISC_RSTOUTNMASKR 0x60 /* RSTOUTn Mask Register */ 291#define ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN (1 << 0) 292#define ARMADAXP_MISC_SSRR 0x64 /* System Soft Reset Register */ 293#define ARMADAXP_MISC_SSRR_GLOBALSOFTRST (1 << 0) 294 295/* 296 * Thermal Sensor and Thermal Management 297 */ 298#define ARMADAXP_TS_BASE (MVSOC_DEVBUS_BASE + 0x82b0) 299#define ARMADAXP_TM_BASE (MVSOC_DEVBUS_BASE + 0x84c0) 300#define ARMADA370_TM_BASE (MVSOC_DEVBUS_BASE + 0x8300) 301 302/* Multiprocessor Interrupt Controller Registers */ 303#define ARMADAXP_MLMB_CFUCONFIG 0x228 304#define ARMADAXP_MLMB_CFUCONFIG_POUTOSL2 (1 << 18) 305#define ARMADAXP_MLMB_CFUCONFIG_POCTOSL2 (1 << 18) 306 307#define ARMADAXP_MLMB_MPIC_BASE 0x20a00 308#define ARMADAXP_MLMB_MPIC_CPU_BASE 0x21800 309#define ARMADAXP_MLMB_MPIC_CTRL 0x0 310#define ARMADAXP_MLMB_MPIC_SOFT_INT 0x4 311#define ARMADAXP_MLMB_MPIC_ERR_CAUSE 0x20 312#define ARMADAXP_MLMB_MPIC_ISE 0x30 313#define ARMADAXP_MLMB_MPIC_ICE 0x34 314#define ARMADAXP_MLMB_MPIC_ISCR_BASE 0x100 315 316#define ARMADAXP_MLMB_MPIC_DOORBELL 0x78 317#define ARMADAXP_MLMB_MPIC_DOORBELL_MASK 0x7c 318#define ARMADAXP_MLMB_MPIC_CTP 0xb0 319#define ARMADAXP_MLMB_MPIC_IIACK 0xb4 320#define ARMADAXP_MLMB_MPIC_ISM 0xb8 321#define ARMADAXP_MLMB_MPIC_ICM 0xbc 322#define ARMADAXP_MLMB_MPIC_ERR_MASK 0xc0 323 324/* Multiprocessor Interrupt Controller Shifts */ 325#define MPIC_CTP_SHIFT 28 /* Global priority level field */ 326#define MPIC_ISCR_SHIFT 24 /* IRQ source priority level field */ 327 328/* Cache Main Control */ 329#define ARMADAXP_L2_BASE 0x8000 330#define ARMADAXP_L2_CTRL 0x100 331#define ARMADAXP_L2_AUX_CTRL 0x104 332#define ARMADAXP_L2_CNTR_CTRL 0x200 333#define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc) 334#define ARMADAXP_L2_INT_CAUSE 0x220 335#define ARMADAXP_L2_CFU 0x228 336#define ARMADAXP_L2_SYNC 0x700 337#define ARMADAXP_L2_STATUS 0x704 338/* Cache maintenance operations */ 339#define ARMADAXP_L2_RANGE_BASE 0x720 340#define ARMADAXP_L2_INV_PHYS 0x770 341#define ARMADAXP_L2_INV_RANGE 0x774 342#define ARMADAXP_L2_INV_IDXWAY 0x778 343#define ARMADAXP_L2_INV_WAY 0x77c 344#define ARMADAXP_L2_BLOCK 0x78c 345#define ARMADAXP_L2_WB_PHYS 0x7b0 346#define ARMADAXP_L2_WB_RANGE 0x7b4 347#define ARMADAXP_L2_WB_IDXWAY 0x7b8 348#define ARMADAXP_L2_WB_WAY 0x7bc 349#define ARMADAXP_L2_WBINV_PHYS 0x7f0 350#define ARMADAXP_L2_WBINV_RANGE 0x7f4 351#define ARMADAXP_L2_WBINV_IDXWAY 0x7f8 352#define ARMADAXP_L2_WBINV_WAY 0x7fc 353 354/* Cache line size */ 355#define ARMADAXP_L2_SIZE (256 * 1024) /* bytes */ 356#define ARMADAXP_L2_LINE_SIZE 32 357#define ARMADAXP_L2_ALIGN (ARMADAXP_L2_LINE_SIZE - 1) 358#define ARMADAXP_L2_WAYS 4 359#define ARMADAXP_L2_WAY_SIZE (ARMADAXP_L2_SIZE / ARMADAXP_L2_WAYS) 360#define ARMADAXP_L2_SETS \ 361 (ARMADAXP_L2_WAY_SIZE / ARMADAXP_L2_LINE_SIZE) 362 363/* ARMADAXP_L2_CTRL */ 364#define L2_CTRL_ENABLE (1 << 0) 365 366/* ARMADAXP_L2_AUX_CTRL */ 367#define L2_AUX_WBWT_MODE_MASK __BITS(1,0) 368#define L2_AUX_WBWT_MODE_BY_ATTR (0 << 0) 369#define L2_AUX_WBWT_MODE_WB (1 << 0) 370#define L2_AUX_WBWT_MODE_WT (2 << 0) 371#define L2_AUX_FLUSH_ON_POWERDOWN __BIT(3) 372#define L2_AUX_ECC_ENABLE __BIT(20) 373#define L2_AUX_PARITY_ENABLE __BIT(21) 374#define L2_AUX_INVAL_UCE __BIT(22) 375#define L2_AUX_FORCE_WA_MASK __BITS(24,23) 376#define L2_AUX_FORCE_WA_BY_ATTR (0 << 23) 377#define L2_AUX_FORCE_WA_DISABLE (1 << 23) 378#define L2_AUX_FORCE_WA_ENABLE (2 << 23) 379#define L2_AUX_FORCE_WA_ENABLE_DT (3 << 23) 380#define L2_AUX_REP_STRAT_MASK (3 << 27) 381#define L2_AUX_REP_STRAT_LFSR (1 << 27) 382#define L2_AUX_REP_STRAT_PLRU (2 << 27) 383#define L2_AUX_REP_STRAT_SEMIPLRU (3 << 27) 384#define L2_AUX_L2_SIZE_MASK (0x03 << 10) 385#define L2_AUX_L2_SIZE_256K (0x00 << 10) 386#define L2_AUX_L2_ASSOC_MASK (0x0f << 13) 387#define L2_AUX_L2_ASSOC_4WAY (0x03 << 13) 388#define L2_AUX_L2_WAY_MASK (0x07 << 17) 389#define L2_AUX_L2_WAY_16K (0x02 << 17) 390#define L2_AUX_L2_WAY_32K (0x03 << 17) 391#define L2_AUX_L2_WAY_64K (0x04 << 17) 392#define L2_AUX_L2_WAY_128K (0x05 << 17) 393#define L2_AUX_L2_WAY_256K (0x06 << 17) 394#define L2_AUX_L2_WAY_512K (0x07 << 17) 395 396#define L2_ALL_WAYS 0xffffffff 397 398/* 399 * PCI-Express Interface Registers 400 */ 401#define ARMADAXP_PEX01_BASE (MVSOC_PEX_BASE + 0x4000) 402#define ARMADAXP_PEX02_BASE (MVSOC_PEX_BASE + 0x8000) 403#define ARMADAXP_PEX03_BASE (MVSOC_PEX_BASE + 0xc000) 404#define ARMADAXP_PEX10_BASE (UNITID2PHYS(PEX1)) 405#define ARMADAXP_PEX11_BASE (ARMADAXP_PEX10_BASE + 0x4000) 406#define ARMADAXP_PEX12_BASE (ARMADAXP_PEX10_BASE + 0x8000) 407#define ARMADAXP_PEX13_BASE (ARMADAXP_PEX10_BASE + 0xc000) 408#define ARMADAXP_PEX2_BASE (UNITID2PHYS(PEX2) + 0x2000) 409#define ARMADAXP_PEX3_BASE (UNITID2PHYS(PEX3) + 0x2000) 410 411/* 412 * USB 2.0 Interface Registers 413 */ 414#define ARMADAXP_USB_BASE (UNITID2PHYS(USB)) /* 0x50000 */ 415#define ARMADAXP_USB0_BASE (ARMADAXP_USB_BASE + 0x0000) 416#define ARMADAXP_USB1_BASE (ARMADAXP_USB_BASE + 0x1000) 417#define ARMADAXP_USB2_BASE (ARMADAXP_USB_BASE + 0x2000) 418 419/* 420 * XOR Engine Registers 421 */ 422#define ARMADAXP_XORE0_BASE (UNITID2PHYS(XORE0)) /* 0x60000 */ 423#define ARMADAXP_XORE1_BASE (UNITID2PHYS(XORE1)) /* 0xf0000 */ 424 425/* 426 * Gigabit Ethernet Registers 427 */ 428#define ARMADAXP_GBE0_BASE (UNITID2PHYS(GBE0)) /* 0x70000 */ 429#define ARMADAXP_GBE1_BASE (ARMADAXP_GBE0_BASE + 0x4000) 430#define ARMADAXP_GBE2_BASE (UNITID2PHYS(GBE2)) /* 0x30000 */ 431#define ARMADAXP_GBE3_BASE (ARMADAXP_GBE2_BASE + 0x4000) 432 433/* 434 * Precise Time Protocol (PTP) Registers 435 */ 436#define ARMADAXP_PTP_BASE (UNITID2PHYS(GBE0)) /* 0x7c000 */ 437 438/* 439 * Cryptographic Engine and Security Accelerator Registers 440 */ 441#define ARMADAXP_CESA0_BASE (UNITID2PHYS(CRYPT) + 0xd000) /* 0x9d000 */ 442#define ARMADAXP_CESA1_BASE (UNITID2PHYS(CRYPT) + 0xf000) /* 0x9f000 */ 443 444#define ARMADAXP_XPSEC0_BASE (UNITID2PHYS(CRYPT) + 0x0000) /* 0x90000 */ 445#define ARMADAXP_XPSEC1_BASE (UNITID2PHYS(CRYPT) + 0x2000) /* 0x92000 */ 446 447/* 448 * Serial-ATA Host Controller (SATAHC) Registers 449 */ 450#define ARMADAXP_SATAHC_BASE (UNITID2PHYS(SATA)) /* 0xa0000 */ 451 452/* 453 * Buffer Management Controller Registers 454 */ 455#define ARMADAXP_BMC_BASE (UNITID2PHYS(BM)) /* 0xc0000 */ 456 457/* 458 * NAND Flash Controller Version 2.0 Registers 459 */ 460#define ARMADAXP_NAND_BASE (UINTID2PHYS(NAND)) 461 462/* 463 * PnC Unit Registers 464 */ 465#define ARMADAXP_PNC_BASE (UNITID2PHYS(PNC)) /* 0xc8000 */ 466 467/* 468 * SDIO Registers 469 */ 470#define ARMADAXP_SDIO_BASE (UNITID2PHYS(SDIO) + 0x4000) /* 0xd4000 */ 471 472/* 473 * Liquid Crystal Display Registers 474 */ 475#define ARMADAXP_LCD_BASE (UNITID2PHYS(LCD)) /* 0xe0000 */ 476 477#endif /* _ARMADAXPREG_H_ */ 478