fix typos in comments.

fix various typos, mainly in comments.

Initialise the windows and allow access to PCI Express port 1 first lane.

Allows xhci(4) to attach in the MV78230 based Lenovo ix4-300d

mvpex1 at mvsoc0 unit 4 offset 0x80000-0x81fff irq 62: Marvell PCI Express Interface
pci1 at mvpex1
xhci0 at pci1 dev 1 function 0: vendor 1033 product 0194 (rev. 0x04)
xhci0: interrupting at interrupt pin INTA#
usb3 at xhci0: USB revision 3.0
usb4 at xhci0: USB revision 2.0

branches: 1.7.2;
Add register macros.
And reorder registers.
Also remove white-spaces.

branches: 1.6.2;
Add mvsocts to mvsoc_periph for Armada XP.

add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function.
some versions of u-boot initializes the address decoder incorrectly(probably
these values are come from Kirkwood SoC or older.) the codes generates
SoC's default address spaces and some modifications for NetBSD's assumption.

add error interrupt definitions, interrupt name strings for 'vmstat -e',
verbose output of Mbus settings for such low-level debugging of SoC.

add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.

implement L2 cache maintenance operations of ARMADA XP.
the L2 cahce maintenance operations are defined on SoC internal registers.

branches: 1.2.4; 1.2.6; 1.2.10; 1.2.12;
Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().

Move armadaxpreg.h into arm/marvell.
And add some defines and reorder.

fix various typos, mainly in comments.

Initialise the windows and allow access to PCI Express port 1 first lane.

Allows xhci(4) to attach in the MV78230 based Lenovo ix4-300d

mvpex1 at mvsoc0 unit 4 offset 0x80000-0x81fff irq 62: Marvell PCI Express Interface
pci1 at mvpex1
xhci0 at pci1 dev 1 function 0: vendor 1033 product 0194 (rev. 0x04)
xhci0: interrupting at interrupt pin INTA#
usb3 at xhci0: USB revision 3.0
usb4 at xhci0: USB revision 2.0

branches: 1.7.2;
Add register macros.
And reorder registers.
Also remove white-spaces.

branches: 1.6.2;
Add mvsocts to mvsoc_periph for Armada XP.

add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function.
some versions of u-boot initializes the address decoder incorrectly(probably
these values are come from Kirkwood SoC or older.) the codes generates
SoC's default address spaces and some modifications for NetBSD's assumption.

add error interrupt definitions, interrupt name strings for 'vmstat -e',
verbose output of Mbus settings for such low-level debugging of SoC.

add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.

implement L2 cache maintenance operations of ARMADA XP.
the L2 cahce maintenance operations are defined on SoC internal registers.

branches: 1.2.4; 1.2.6; 1.2.10; 1.2.12;
Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().

Move armadaxpreg.h into arm/marvell.
And add some defines and reorder.

Initialise the windows and allow access to PCI Express port 1 first lane.

Allows xhci(4) to attach in the MV78230 based Lenovo ix4-300d

mvpex1 at mvsoc0 unit 4 offset 0x80000-0x81fff irq 62: Marvell PCI Express Interface
pci1 at mvpex1
xhci0 at pci1 dev 1 function 0: vendor 1033 product 0194 (rev. 0x04)
xhci0: interrupting at interrupt pin INTA#
usb3 at xhci0: USB revision 3.0
usb4 at xhci0: USB revision 2.0

Add register macros.
And reorder registers.
Also remove white-spaces.

Add mvsocts to mvsoc_periph for Armada XP.

add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function.
some versions of u-boot initializes the address decoder incorrectly(probably
these values are come from Kirkwood SoC or older.) the codes generates
SoC's default address spaces and some modifications for NetBSD's assumption.

add error interrupt definitions, interrupt name strings for 'vmstat -e',
verbose output of Mbus settings for such low-level debugging of SoC.

add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.

implement L2 cache maintenance operations of ARMADA XP.
the L2 cahce maintenance operations are defined on SoC internal registers.

branches: 1.2.4; 1.2.6; 1.2.10; 1.2.12;
Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().

Move armadaxpreg.h into arm/marvell.
And add some defines and reorder.

Add register macros.
And reorder registers.
Also remove white-spaces.

Add mvsocts to mvsoc_periph for Armada XP.

add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function.
some versions of u-boot initializes the address decoder incorrectly(probably
these values are come from Kirkwood SoC or older.) the codes generates
SoC's default address spaces and some modifications for NetBSD's assumption.

add error interrupt definitions, interrupt name strings for 'vmstat -e',
verbose output of Mbus settings for such low-level debugging of SoC.

add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.

implement L2 cache maintenance operations of ARMADA XP.
the L2 cahce maintenance operations are defined on SoC internal registers.

branches: 1.2.4; 1.2.6; 1.2.10; 1.2.12;
Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().

Move armadaxpreg.h into arm/marvell.
And add some defines and reorder.

Add mvsocts to mvsoc_periph for Armada XP.

add ARMADA XP's Soc internal bus(Mbus) address decoder initialization function.
some versions of u-boot initializes the address decoder incorrectly(probably
these values are come from Kirkwood SoC or older.) the codes generates
SoC's default address spaces and some modifications for NetBSD's assumption.

add error interrupt definitions, interrupt name strings for 'vmstat -e',
verbose output of Mbus settings for such low-level debugging of SoC.

add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.

implement L2 cache maintenance operations of ARMADA XP.
the L2 cahce maintenance operations are defined on SoC internal registers.

branches: 1.2.4; 1.2.6; 1.2.10; 1.2.12;
Move Misc Registers from mvsocreg.h to armadaxpreg.h. These registers only
Armada XP. The misc_base initializes in initarm() instead of mvsoc_bootstrap().

Move armadaxpreg.h into arm/marvell.
And add some defines and reorder.