1/*	$NetBSD: ixp12x0var.h,v 1.10 2012/10/27 17:17:39 chs Exp $ */
2/*
3 * Copyright (c) 2002
4 *	Ichiro FUKUHARA <ichiro@ichiro.org>.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef _IXP12X0VAR_H_
30#define _IXP12X0VAR_H_
31
32#include <sys/conf.h>
33#include <sys/device.h>
34#include <sys/queue.h>
35
36#include <sys/bus.h>
37
38#include <dev/pci/pcivar.h>
39
40struct ixp12x0_softc {
41	device_t sc_dev;
42	bus_space_tag_t sc_iot;
43
44	/* Handles for the PCI */
45	bus_space_handle_t sc_pci_ioh;		/* PCI CSR */
46	bus_space_handle_t sc_conf0_ioh;	/* PCI Configuration 0 */
47	bus_space_handle_t sc_conf1_ioh;	/* PCI Configuration 1 */
48
49	/* DMA, and PCI chipset */
50        struct arm32_bus_dma_tag ia_pci_dmat;
51        struct arm32_pci_chipset ia_pci_chipset;
52
53	/* DMA window info for PCI DMA. */
54	struct arm32_dma_range ia_pci_dma_range;
55
56	/* GPIO */
57};
58
59struct intrhand {
60	TAILQ_ENTRY(intrhand) ih_list;	/* link on intrq list */
61	int (*ih_func)(void *);		/* interrupt handler */
62	void *ih_arg;			/* arg for handler */
63	int ih_ipl;			/* IPL_* */
64	int ih_irq;			/* IRQ number */
65};
66
67#define	IRQNAMESIZE	sizeof("ixpintr ipl xxx")
68
69struct intrq {
70	TAILQ_HEAD(, intrhand) iq_list;	/* handler list */
71	struct evcnt iq_ev;		/* event counter */
72	uint32_t iq_mask;		/* IRQs to mask while handling */
73	uint32_t iq_pci_mask;		/* PCI IRQs to mask while handling */
74	uint32_t iq_levels;		/* IPL_*'s this IRQ has */
75	char iq_name[IRQNAMESIZE];	/* interrupt name */
76	int iq_ist;			/* share type */
77};
78
79struct pmap_ent {
80	const char*	msg;
81	vaddr_t		va;
82	paddr_t		pa;
83	vsize_t		sz;
84	int		prot;
85	int		cache;
86};
87
88extern struct bus_space	ixp12x0_bs_tag;
89
90void	ixp12x0_pci_init(pci_chipset_tag_t, void *);
91void	ixp12x0_pci_dma_init(struct ixp12x0_softc *);
92void	ixp12x0_attach(struct ixp12x0_softc *);
93void	ixp12x0_intr_init(void);
94void	*ixp12x0_intr_establish(int irq, int ipl, int (*)(void *), void *);
95void	ixp12x0_intr_disestablish(void *);
96void	ixp12x0_pmap_chunk_table(vaddr_t l1pt, struct pmap_ent* m);
97void	ixp12x0_pmap_io_reg(vaddr_t l1pt);
98void	ixp12x0_reset(void);
99
100#endif /* _IXP12X0VAR_H_ */
101