lock.h revision 1.34 
1/*	$NetBSD: lock.h,v 1.34 2019/11/29 20:05:19 riastradh Exp $	*/
2
3/*-
4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Machine-dependent spin lock operations.
34 *
35 * NOTE: The SWP insn used here is available only on ARM architecture
36 * version 3 and later (as well as 2a).  What we are going to do is
37 * expect that the kernel will trap and emulate the insn.  That will
38 * be slow, but give us the atomicity that we need.
39 */
40
41#ifndef _ARM_LOCK_H_
42#define	_ARM_LOCK_H_
43
44static __inline int
45__SIMPLELOCK_LOCKED_P(const __cpu_simple_lock_t *__ptr)
46{
47	return *__ptr == __SIMPLELOCK_LOCKED;
48}
49
50static __inline int
51__SIMPLELOCK_UNLOCKED_P(const __cpu_simple_lock_t *__ptr)
52{
53	return *__ptr == __SIMPLELOCK_UNLOCKED;
54}
55
56static __inline void
57__cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr)
58{
59	*__ptr = __SIMPLELOCK_UNLOCKED;
60}
61
62static __inline void
63__cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
64{
65	*__ptr = __SIMPLELOCK_LOCKED;
66}
67
68#ifdef _KERNEL
69/* XXX Formerly included for obsolete mb_* API, maybe no longer needed.  */
70#include <arm/cpufunc.h>
71#endif
72
73#ifdef _ARM_ARCH_6
74static __inline unsigned int
75__arm_load_exclusive(__cpu_simple_lock_t *__alp)
76{
77	unsigned int __rv;
78	if (/*CONSTCOND*/sizeof(*__alp) == 1) {
79		__asm __volatile("ldrexb\t%0,[%1]" : "=r"(__rv) : "r"(__alp));
80	} else {
81		__asm __volatile("ldrex\t%0,[%1]" : "=r"(__rv) : "r"(__alp));
82	}
83	return __rv;
84}
85
86/* returns 0 on success and 1 on failure */
87static __inline unsigned int
88__arm_store_exclusive(__cpu_simple_lock_t *__alp, unsigned int __val)
89{
90	unsigned int __rv;
91	if (/*CONSTCOND*/sizeof(*__alp) == 1) {
92		__asm __volatile("strexb\t%0,%1,[%2]"
93		    : "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
94	} else {
95		__asm __volatile("strex\t%0,%1,[%2]"
96		    : "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
97	}
98	return __rv;
99}
100#elif defined(_KERNEL)
101static __inline unsigned char
102__swp(unsigned char __val, __cpu_simple_lock_t *__ptr)
103{
104	uint32_t __val32;
105	__asm volatile("swpb	%0, %1, [%2]"
106	    : "=&r" (__val32) : "r" (__val), "r" (__ptr) : "memory");
107	return __val32;
108}
109#else
110/*
111 * On MP Cortex, SWP no longer guarantees atomic results.  Thus we pad
112 * out SWP so that when the cpu generates an undefined exception we can replace
113 * the SWP/MOV instructions with the right LDREX/STREX instructions.
114 *
115 * This is why we force the SWP into the template needed for LDREX/STREX
116 * including the extra instructions and extra register for testing the result.
117 */
118static __inline int
119__swp(int __val, __cpu_simple_lock_t *__ptr)
120{
121	int __tmp, __rv;
122	__asm volatile(
123#if 1
124	"1:\t"	"swp	%[__rv], %[__val], [%[__ptr]]"
125	"\n\t"	"b	2f"
126#else
127	"1:\t"	"ldrex	%[__rv],[%[__ptr]]"
128	"\n\t"	"strex	%[__tmp],%[__val],[%[__ptr]]"
129#endif
130	"\n\t"	"cmp	%[__tmp],#0"
131	"\n\t"	"bne	1b"
132	"\n"	"2:"
133	    : [__rv] "=&r" (__rv), [__tmp] "=&r" (__tmp)
134	    : [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
135	return __rv;
136}
137#endif /* !_ARM_ARCH_6 */
138
139static __inline void
140__arm_membar_producer(void)
141{
142#ifdef _ARM_ARCH_7
143	__asm __volatile("dsb" ::: "memory");
144#elif defined(_ARM_ARCH_6)
145	__asm __volatile("mcr\tp15,0,%0,c7,c10,4" :: "r"(0) : "memory");
146#endif
147}
148
149static __inline void
150__arm_membar_consumer(void)
151{
152#ifdef _ARM_ARCH_7
153	__asm __volatile("dmb" ::: "memory");
154#elif defined(_ARM_ARCH_6)
155	__asm __volatile("mcr\tp15,0,%0,c7,c10,5" :: "r"(0) : "memory");
156#endif
157}
158
159static __inline void __unused
160__cpu_simple_lock_init(__cpu_simple_lock_t *__alp)
161{
162
163	*__alp = __SIMPLELOCK_UNLOCKED;
164	__arm_membar_producer();
165}
166
167#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
168static __inline void __unused
169__cpu_simple_lock(__cpu_simple_lock_t *__alp)
170{
171#ifdef _ARM_ARCH_6
172	__arm_membar_consumer();
173	do {
174		/* spin */
175	} while (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED
176		 || __arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
177	__arm_membar_producer();
178#else
179	while (__swp(__SIMPLELOCK_LOCKED, __alp) != __SIMPLELOCK_UNLOCKED)
180		continue;
181#endif
182}
183#else
184void __cpu_simple_lock(__cpu_simple_lock_t *);
185#endif
186
187#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
188static __inline int __unused
189__cpu_simple_lock_try(__cpu_simple_lock_t *__alp)
190{
191#ifdef _ARM_ARCH_6
192	__arm_membar_consumer();
193	do {
194		if (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED) {
195			return 0;
196		}
197	} while (__arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
198	__arm_membar_producer();
199	return 1;
200#else
201	return (__swp(__SIMPLELOCK_LOCKED, __alp) == __SIMPLELOCK_UNLOCKED);
202#endif
203}
204#else
205int __cpu_simple_lock_try(__cpu_simple_lock_t *);
206#endif
207
208static __inline void __unused
209__cpu_simple_unlock(__cpu_simple_lock_t *__alp)
210{
211
212#ifdef _ARM_ARCH_8
213	if (sizeof(*__alp) == 1) {
214		__asm __volatile("stlb\t%0, [%1]"
215		    :: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
216	} else {
217		__asm __volatile("stl\t%0, [%1]"
218		    :: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
219	}
220#else
221	__arm_membar_consumer();
222	*__alp = __SIMPLELOCK_UNLOCKED;
223	__arm_membar_producer();
224#endif
225}
226
227#endif /* _ARM_LOCK_H_ */
228