1/*	$NetBSD: imx51_ccmvar.h,v 1.2 2014/03/22 09:46:33 hkenken Exp $	*/
2/*
3 * Copyright (c) 2012  Genetec Corporation.  All rights reserved.
4 * Written by Hashimoto Kenichi for Genetec Corporation.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
18 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef	_ARM_IMX_IMX51_CCMVAR_H_
29#define	_ARM_IMX_IMX51_CCMVAR_H_
30
31enum imx51_clock {
32	IMX51CLK_FPM,
33	IMX51CLK_PLL1,
34	IMX51CLK_PLL2,
35	IMX51CLK_PLL3,
36	IMX51CLK_PLL1SW,
37	IMX51CLK_PLL2SW,
38	IMX51CLK_PLL3SW,
39	IMX51CLK_PLL1STEP,
40	IMX51CLK_LP_APM,
41	IMX51CLK_ARM_ROOT,
42	IMX51CLK_MAIN_BUS_CLK_SRC,	/* XXX */
43	IMX51CLK_MAIN_BUS_CLK,
44	IMX51CLK_EMI_SLOW_CLK_ROOT,
45	IMX51CLK_ENFC_CLK_ROOT,
46	IMX51CLK_AHB_CLK_ROOT,
47	IMX51CLK_IPG_CLK_ROOT,
48	IMX51CLK_PERCLK_ROOT,
49	IMX51CLK_DDR_CLK_ROOT,
50	IMX51CLK_ARM_AXI_CLK_ROOT,
51	IMX51CLK_ARM_AXI_A_CLK,
52	IMX51CLK_ARM_AXI_B_CLK,
53	IMX51CLK_IPU_HSP_CLK_ROOT,
54	IMX51CLK_CKIL_SYNC_CLK_ROOT,
55	IMX51CLK_USBOH3_CLK_ROOT,
56	IMX51CLK_ESDHC1_CLK_ROOT,
57	IMX51CLK_ESDHC2_CLK_ROOT,
58	IMX51CLK_ESDHC3_CLK_ROOT,
59	IMX51CLK_ESDHC4_CLK_ROOT,
60	IMX51CLK_UART_CLK_ROOT,
61	IMX51CLK_SSI1_CLK_ROOT,
62	IMX51CLK_SSI2_CLK_ROOT,
63	IMX51CLK_SSI_EXT1_CLK_ROOT,
64	IMX51CLK_SSI_EXT2_CLK_ROOT,
65	IMX51CLK_USB_PHY_CLK_ROOT,
66	IMX51CLK_TVE_216_54_CLK_ROOT,
67	IMX51CLK_DI_CLK_ROOT,
68	IMX51CLK_SPDIF0_CLK_ROOT,
69	IMX51CLK_SPDIF1_CLK_ROOT,
70	IMX51CLK_CSPI_CLK_ROOT,
71	IMX51CLK_WRCK_CLK_ROOT,
72	IMX51CLK_LPSR_CLK_ROOT,
73	IMX51CLK_PGC_CLK_ROOT,
74#if IMX50
75	IMX50CLK_PFD0_CLK_ROOT,
76	IMX50CLK_PFD1_CLK_ROOT,
77	IMX50CLK_PFD2_CLK_ROOT,
78	IMX50CLK_PFD3_CLK_ROOT,
79	IMX50CLK_PFD4_CLK_ROOT,
80	IMX50CLK_PFD5_CLK_ROOT,
81	IMX50CLK_PFD6_CLK_ROOT,
82	IMX50CLK_PFD7_CLK_ROOT,
83#endif
84};
85
86u_int imx51_get_clock(enum imx51_clock);
87void imx51_clk_gating(int, int);
88void imx51_clk_rate(int, int, int);
89
90#endif	/* _ARM_IMX_IMX51_CCMVAR_H_ */
91