1/* $Id: imx23_pinctrl.c,v 1.6 2021/08/07 16:18:44 thorpej Exp $ */ 2 3/* 4* Copyright (c) 2013 The NetBSD Foundation, Inc. 5* All rights reserved. 6* 7* This code is derived from software contributed to The NetBSD Foundation 8* by Petri Laakso. 9* 10* Redistribution and use in source and binary forms, with or without 11* modification, are permitted provided that the following conditions 12* are met: 13* 1. Redistributions of source code must retain the above copyright 14* notice, this list of conditions and the following disclaimer. 15* 2. Redistributions in binary form must reproduce the above copyright 16* notice, this list of conditions and the following disclaimer in the 17* documentation and/or other materials provided with the distribution. 18* 19* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29* POSSIBILITY OF SUCH DAMAGE. 30*/ 31 32#include <sys/param.h> 33#include <sys/types.h> 34#include <sys/bus.h> 35#include <sys/cdefs.h> 36#include <sys/device.h> 37#include <sys/errno.h> 38#include <sys/gpio.h> 39 40#include <dev/gpio/gpiovar.h> 41 42#include <arm/imx/imx23_pinctrlreg.h> 43#include <arm/imx/imx23_pinctrlvar.h> 44#include <arm/imx/imx23var.h> 45 46#define GPIO_PINS 96 47 48typedef struct imx23_pinctrl_softc { 49 device_t sc_dev; 50 bus_space_tag_t sc_iot; 51 bus_space_handle_t sc_hdl; 52 struct gpio_chipset_tag gc; 53 gpio_pin_t pins[GPIO_PINS]; 54} *imx23_pinctrl_softc_t; 55 56static int imx23_pinctrl_match(device_t, cfdata_t, void *); 57static void imx23_pinctrl_attach(device_t, device_t, void *); 58static int imx23_pinctrl_activate(device_t, enum devact); 59 60#if notyet 61static void imx23_pinctrl_reset(struct imx23_pinctrl_softc *); 62#endif 63static void imx23_pinctrl_init(struct imx23_pinctrl_softc *); 64 65static int imx23_pinctrl_gp_gc_open(void *, device_t); 66static void imx23_pinctrl_gp_gc_close(void *, device_t); 67static int imx23_pinctrl_gp_pin_read(void *, int); 68static void imx23_pinctrl_gp_pin_write(void *, int, int); 69static void imx23_pinctrl_gp_pin_ctl(void *, int, int); 70 71static imx23_pinctrl_softc_t _sc = NULL; 72 73CFATTACH_DECL3_NEW(imx23_pinctrl, 74 sizeof(struct imx23_pinctrl_softc), 75 imx23_pinctrl_match, 76 imx23_pinctrl_attach, 77 NULL, 78 imx23_pinctrl_activate, 79 NULL, 80 NULL, 81 0 82); 83 84#define GPIO_PIN_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_INOUT | \ 85 GPIO_PIN_PULLUP | GPIO_PIN_SET) 86 87/* 88 * Supported capabilities for each GPIO pin. 89 */ 90const static int pin_caps[GPIO_PINS] = { 91 /* 92 * HW_PINCTRL_MUXSEL0 93 */ 94 /* PIN 0 */ 95 GPIO_PIN_CAP, 96 /* PIN 1 */ 97 GPIO_PIN_CAP, 98 /* PIN 2 */ 99 GPIO_PIN_CAP, 100 /* PIN 3 */ 101 GPIO_PIN_CAP, 102 /* PIN 4 */ 103 GPIO_PIN_CAP, 104 /* PIN 5 */ 105 GPIO_PIN_CAP, 106 /* PIN 6 */ 107 GPIO_PIN_CAP, 108 /* PIN 7 */ 109 GPIO_PIN_CAP, 110 /* PIN 8 */ 111 GPIO_PIN_CAP, 112 /* PIN 9 */ 113 GPIO_PIN_CAP, 114 /* PIN 10 */ 115 GPIO_PIN_CAP, 116 /* PIN 11 */ 117 GPIO_PIN_CAP, 118 /* PIN 12 */ 119 GPIO_PIN_CAP, 120 /* PIN 13 */ 121 GPIO_PIN_CAP, 122 /* PIN 14 */ 123 GPIO_PIN_CAP, 124 /* PIN 15 */ 125 GPIO_PIN_CAP, 126 /* 127 * HW_PINCTRL_MUXSEL1 128 */ 129 /* PIN 16 */ 130 GPIO_PIN_CAP, 131 /* PIN 17 */ 132 0, /* Reserved for powering OLinuXino MAXI/MINI USB hub. */ 133 /* PIN 18 */ 134 GPIO_PIN_CAP, 135 /* PIN 19 */ 136 GPIO_PIN_CAP, 137 /* PIN 20 */ 138 GPIO_PIN_CAP, 139 /* PIN 21 */ 140 GPIO_PIN_CAP, 141 /* PIN 22 */ 142 GPIO_PIN_CAP, 143 /* PIN 23 */ 144 GPIO_PIN_CAP, 145 /* PIN 24 */ 146 GPIO_PIN_CAP, 147 /* PIN 25 */ 148 GPIO_PIN_CAP, 149 /* PIN 26 */ 150 GPIO_PIN_CAP, 151 /* PIN 27 */ 152 GPIO_PIN_CAP, 153 /* PIN 28 */ 154 GPIO_PIN_CAP, 155 /* PIN 29 */ 156 GPIO_PIN_CAP, 157 /* PIN 30 */ 158 GPIO_PIN_CAP, 159 /* PIN 31 */ 160 GPIO_PIN_CAP, 161 /* 162 * HW_PINCTRL_MUXSEL2 163 */ 164 /* PIN 32 */ 165 GPIO_PIN_CAP, 166 /* PIN 33 */ 167 GPIO_PIN_CAP, 168 /* PIN 34 */ 169 GPIO_PIN_CAP, 170 /* PIN 35 */ 171 GPIO_PIN_CAP, 172 /* PIN 36 */ 173 GPIO_PIN_CAP, 174 /* PIN 37 */ 175 GPIO_PIN_CAP, 176 /* PIN 38 */ 177 GPIO_PIN_CAP, 178 /* PIN 39 */ 179 GPIO_PIN_CAP, 180 /* PIN 40 */ 181 GPIO_PIN_CAP, 182 /* PIN 41 */ 183 GPIO_PIN_CAP, 184 /* PIN 42 */ 185 GPIO_PIN_CAP, 186 /* PIN 43 */ 187 GPIO_PIN_CAP, 188 /* PIN 44 */ 189 GPIO_PIN_CAP, 190 /* PIN 45 */ 191 GPIO_PIN_CAP, 192 /* PIN 46 */ 193 GPIO_PIN_CAP, 194 /* PIN 47 */ 195 GPIO_PIN_CAP, 196 /* 197 * HW_PINCTRL_MUXSEL3 198 */ 199 /* PIN 48 */ 200 GPIO_PIN_CAP, 201 /* PIN 49 */ 202 GPIO_PIN_CAP, 203 /* PIN 50 */ 204 GPIO_PIN_CAP, 205 /* PIN 51 */ 206 GPIO_PIN_CAP, 207 /* PIN 52 */ 208 GPIO_PIN_CAP, 209 /* PIN 53 */ 210 GPIO_PIN_CAP, 211 /* PIN 54 */ 212 GPIO_PIN_CAP, 213 /* PIN 55 */ 214 GPIO_PIN_CAP, 215 /* PIN 56 */ 216 GPIO_PIN_CAP, 217 /* PIN 57 */ 218 GPIO_PIN_CAP, 219 /* PIN 58 */ 220 GPIO_PIN_CAP, 221 /* PIN 59 */ 222 GPIO_PIN_CAP, 223 /* PIN 60 */ 224 GPIO_PIN_CAP, 225 /* PIN 61 */ 226 GPIO_PIN_CAP, 227 /* PIN 62 */ 228 GPIO_PIN_CAP, 229 /* PIN 63 */ 230 0, /* Reserved. */ 231 /* 232 * HW_PINCTRL_MUXSEL4 233 */ 234 /* PIN 64 */ 235 GPIO_PIN_CAP, 236 /* PIN 65 */ 237 GPIO_PIN_CAP, 238 /* PIN 66 */ 239 GPIO_PIN_CAP, 240 /* PIN 67 */ 241 GPIO_PIN_CAP, 242 /* PIN 68 */ 243 GPIO_PIN_CAP, 244 /* PIN 69 */ 245 GPIO_PIN_CAP, 246 /* PIN 70 */ 247 GPIO_PIN_CAP, 248 /* PIN 71 */ 249 GPIO_PIN_CAP, 250 /* PIN 72 */ 251 GPIO_PIN_CAP, 252 /* PIN 73 */ 253 0, /* From this on reserved for EMI (DRAM) pins. */ 254 /* PIN 74 */ 255 0, 256 /* PIN 75 */ 257 0, 258 /* PIN 76 */ 259 0, 260 /* PIN 77 */ 261 0, 262 /* PIN 78 */ 263 0, 264 /* PIN 79 */ 265 0, 266 /* 267 * HW_PINCTRL_MUXSEL5 268 */ 269 /* PIN 80 */ 270 0, 271 /* PIN 81 */ 272 0, 273 /* PIN 82 */ 274 0, 275 /* PIN 83 */ 276 0, 277 /* PIN 84 */ 278 0, 279 /* PIN 85 */ 280 0, 281 /* PIN 86 */ 282 0, 283 /* PIN 87 */ 284 0, 285 /* PIN 88 */ 286 0, 287 /* PIN 89 */ 288 0, 289 /* PIN 90 */ 290 0, 291 /* PIN 91 */ 292 0, 293 /* PIN 92 */ 294 0, 295 /* PIN 93 */ 296 0, 297 /* PIN 94 */ 298 0, 299 /* PIN 95 */ 300 0 301}; 302 303#define PINCTRL_RD(sc, reg) \ 304 bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg)) 305#define PINCTRL_WR(sc, reg, val) \ 306 bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val)) 307 308/* 309 * Macros to map pin numbers to registers and bit fields. 310 */ 311#define MUXSEL_REG_SIZE 0x10 312#define PIN2MUXSEL_REG(pin) \ 313 ((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0) 314#define PIN2MUXSEL_SET_REG(pin) \ 315 ((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0_SET) 316#define PIN2MUXSEL_CLR_REG(pin) \ 317 ((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0_CLR) 318#define PIN2MUXSEL_MASK(pin) (3<<(pin % 16 * 2)) 319 320#define DRIVE_REG_SIZE 0x10 321#define PIN2DRIVE_REG(pin) \ 322 ((pin / 8) * DRIVE_REG_SIZE + HW_PINCTRL_DRIVE0) 323#define PIN2DRIVE_SET_REG(pin) \ 324 ((pin / 8) * DRIVE_REG_SIZE + HW_PINCTRL_DRIVE0_SET) 325#define PIN2DRIVE_CLR_REG(pin) \ 326 ((pin / 8) * DRIVE_REG_SIZE + HW_PINCTRL_DRIVE0_CLR) 327#define PIN2DRIVE_MASK(pin) (3<<(pin % 8 * 4)) 328 329#define PULL_REG_SIZE 0x10 330#define PIN2PULL_REG(pin) \ 331 ((pin / 32) * PULL_REG_SIZE + HW_PINCTRL_PULL0) 332#define PIN2PULL_SET_REG(pin) \ 333 ((pin / 32) * PULL_REG_SIZE + HW_PINCTRL_PULL0_SET) 334#define PIN2PULL_CLR_REG(pin) \ 335 ((pin / 32) * PULL_REG_SIZE + HW_PINCTRL_PULL0_CLR) 336#define PIN2PULL_MASK(pin) (1<<(pin % 32)) 337 338#define DOUT_REG_SIZE 0x10 339#define PIN2DOUT_REG(pin) \ 340 ((pin / 32) * DOUT_REG_SIZE + HW_PINCTRL_DOUT0) 341#define PIN2DOUT_SET_REG(pin) \ 342 ((pin / 32) * DOUT_REG_SIZE + HW_PINCTRL_DOUT0_SET) 343#define PIN2DOUT_CLR_REG(pin) \ 344 ((pin / 32) * DOUT_REG_SIZE + HW_PINCTRL_DOUT0_CLR) 345#define PIN2DOUT_MASK(pin) (1<<(pin % 32)) 346 347#define DIN_REG_SIZE 0x10 348#define PIN2DIN_REG(pin) ((pin / 32) * DIN_REG_SIZE + HW_PINCTRL_DIN0) 349#define PIN2DIN_MASK(pin) (1<<(pin % 32)) 350 351#define DOE_REG_SIZE 0x10 352#define PIN2DOE_REG(pin) \ 353 ((pin / 32) * DOE_REG_SIZE + HW_PINCTRL_DOE0) 354#define PIN2DOE_SET_REG(pin) \ 355 ((pin / 32) * DOE_REG_SIZE + HW_PINCTRL_DOE0_SET) 356#define PIN2DOE_CLR_REG(pin) \ 357 ((pin / 32) * DOE_REG_SIZE + HW_PINCTRL_DOE0_CLR) 358#define PIN2DOE_MASK(pin) (1<<(pin % 32)) 359 360#define DRIVE_STRENGTH_4MA 0 361#define DRIVE_STRENGTH_8MA 1 362#define DRIVE_STRENGTH_12MA 2 363 364#define MUXEL_GPIO_MODE 3 365 366#define PINCTRL_SOFT_RST_LOOP 455 /* At least 1 us ... */ 367 368static int 369imx23_pinctrl_match(device_t parent, cfdata_t match, void *aux) 370{ 371 struct apb_attach_args *aa = aux; 372 373 if ((aa->aa_addr == HW_PINCTRL_BASE) && 374 (aa->aa_size == HW_PINCTRL_SIZE)) 375 return 1; 376 377 return 0; 378} 379 380static void 381imx23_pinctrl_attach(device_t parent, device_t self, void *aux) 382{ 383 struct imx23_pinctrl_softc *sc = device_private(self); 384 struct apb_attach_args *aa = aux; 385 static int imx23_pinctrl_attached = 0; 386 387 sc->sc_dev = self; 388 sc->sc_iot = aa->aa_iot; 389 390 if (imx23_pinctrl_attached) { 391 aprint_error_dev(sc->sc_dev, "already attached\n"); 392 return; 393 } 394 395 if (bus_space_map(sc->sc_iot, aa->aa_addr, aa->aa_size, 0, 396 &sc->sc_hdl)) { 397 aprint_error_dev(sc->sc_dev, "Unable to map bus space\n"); 398 return; 399 } 400 401#if notyet 402 imx23_pinctrl_reset(sc); 403#endif 404 405 imx23_pinctrl_init(sc); 406 407 aprint_normal(": PIN MUX & GPIO\n"); 408 409 /* Set pin capabilities. */ 410 int i; 411 for(i = 0; i < GPIO_PINS; i++) { 412 sc->pins[i].pin_caps = pin_caps[i]; 413 } 414 415 imx23_pinctrl_attached = 1; 416 417 sc->gc.gp_cookie = sc; 418 sc->gc.gp_gc_open = imx23_pinctrl_gp_gc_open; 419 sc->gc.gp_gc_close = imx23_pinctrl_gp_gc_close; 420 sc->gc.gp_pin_read = imx23_pinctrl_gp_pin_read; 421 sc->gc.gp_pin_write = imx23_pinctrl_gp_pin_write; 422 sc->gc.gp_pin_ctl = imx23_pinctrl_gp_pin_ctl; 423 424 struct gpiobus_attach_args gpiobus_aa; 425 gpiobus_aa.gba_gc = &sc->gc; 426 gpiobus_aa.gba_npins = GPIO_PINS; 427 gpiobus_aa.gba_pins = sc->pins; 428 429 config_found(self, &gpiobus_aa, gpiobus_print, CFARGS_NONE); 430 431 return; 432} 433 434static int 435imx23_pinctrl_activate(device_t self, enum devact act) 436{ 437 438 return EOPNOTSUPP; 439} 440 441static void 442imx23_pinctrl_init(struct imx23_pinctrl_softc *sc) 443{ 444 _sc = sc; 445 return; 446} 447 448#if notyet 449/* 450 * Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block" 451 */ 452static void 453imx23_pinctrl_reset(struct imx23_pinctrl_softc *sc) 454{ 455 unsigned int loop; 456 457 /* Prepare for soft-reset by making sure that SFTRST is not currently 458 * asserted. Also clear CLKGATE so we can wait for its assertion below. 459 */ 460 PINCTRL_WR(sc, HW_PINCTRL_CTRL_CLR, HW_PINCTRL_CTRL_SFTRST); 461 462 /* Wait at least a microsecond for SFTRST to deassert. */ 463 loop = 0; 464 while ((PINCTRL_RD(sc, HW_PINCTRL_CTRL) & HW_PINCTRL_CTRL_SFTRST) || 465 (loop < PINCTRL_SOFT_RST_LOOP)) 466 loop++; 467 468 /* Clear CLKGATE so we can wait for its assertion below. */ 469 PINCTRL_WR(sc, HW_PINCTRL_CTRL_CLR, HW_PINCTRL_CTRL_CLKGATE); 470 471 /* Soft-reset the block. */ 472 PINCTRL_WR(sc, HW_PINCTRL_CTRL_SET, HW_PINCTRL_CTRL_SFTRST); 473 474 /* Wait until clock is in the gated state. */ 475 while (!(PINCTRL_RD(sc, HW_PINCTRL_CTRL) & HW_PINCTRL_CTRL_CLKGATE)); 476 477 /* Bring block out of reset. */ 478 PINCTRL_WR(sc, HW_PINCTRL_CTRL_CLR, HW_PINCTRL_CTRL_SFTRST); 479 480 loop = 0; 481 while ((PINCTRL_RD(sc, HW_PINCTRL_CTRL) & HW_PINCTRL_CTRL_SFTRST) || 482 (loop < PINCTRL_SOFT_RST_LOOP)) 483 loop++; 484 485 PINCTRL_WR(sc, HW_PINCTRL_CTRL_CLR, HW_PINCTRL_CTRL_CLKGATE); 486 487 /* Wait until clock is in the NON-gated state. */ 488 while (PINCTRL_RD(sc, HW_PINCTRL_CTRL) & HW_PINCTRL_CTRL_CLKGATE); 489 490 return; 491} 492#endif 493 494/* 495 * Enable external USB transceiver/HUB. 496 * 497 * PIN18/LCD_D17/USB_EN controls reset line of external USB chip on MINI and 498 * MAXI boards. We configure this pin to logic 1. 499 */ 500void 501imx23_pinctrl_en_usb(void) 502{ 503 struct imx23_pinctrl_softc *sc = _sc; 504 505 if (sc == NULL) { 506 aprint_error("imx23_pinctrl is not initialized"); 507 return; 508 } 509 510 imx23_pinctrl_gp_pin_ctl(sc, 17, GPIO_PIN_OUTPUT); 511 delay(1000); 512 imx23_pinctrl_gp_pin_write(sc, 17, 1); 513 514 return; 515} 516 517static int 518imx23_pinctrl_gp_gc_open(void *cookie, device_t dev) 519{ 520 return 0; 521} 522 523static void 524imx23_pinctrl_gp_gc_close(void *cookie, device_t dev) 525{ 526 return; 527} 528 529static int 530imx23_pinctrl_gp_pin_read(void *cookie, int pin) 531{ 532 int value; 533 imx23_pinctrl_softc_t sc = (imx23_pinctrl_softc_t) cookie; 534 535 if (PINCTRL_RD(sc, PIN2DIN_REG(pin)) & PIN2DIN_MASK(pin)) 536 value = 1; 537 else 538 value = 0; 539 540 return value; 541} 542 543static void 544imx23_pinctrl_gp_pin_write(void *cookie, int pin, int value) 545{ 546 imx23_pinctrl_softc_t sc = (imx23_pinctrl_softc_t) cookie; 547 548 if (value) 549 PINCTRL_WR(sc, PIN2DOUT_SET_REG(pin), PIN2DOUT_MASK(pin)); 550 else 551 PINCTRL_WR(sc, PIN2DOUT_CLR_REG(pin), PIN2DOUT_MASK(pin)); 552 553 return; 554} 555 556/* 557 * Configure pin as requested in flags. 558 */ 559static void 560imx23_pinctrl_gp_pin_ctl(void *cookie, int pin, int flags) 561{ 562 imx23_pinctrl_softc_t sc = (imx23_pinctrl_softc_t) cookie; 563 uint32_t tmpr; 564 565 /* Enable GPIO pin. */ 566 tmpr = PINCTRL_RD(sc, PIN2MUXSEL_REG(pin)); 567 tmpr &= ~PIN2MUXSEL_MASK(pin); 568 tmpr |= __SHIFTIN(MUXEL_GPIO_MODE, PIN2MUXSEL_MASK(pin)); 569 PINCTRL_WR(sc, PIN2MUXSEL_REG(pin), tmpr); 570 571 /* Configure pin drive strength. */ 572 tmpr = PINCTRL_RD(sc, PIN2DRIVE_REG(pin)); 573 tmpr &= ~PIN2DRIVE_MASK(pin); 574 tmpr |= __SHIFTIN(DRIVE_STRENGTH_4MA, PIN2DRIVE_MASK(pin)); 575 PINCTRL_WR(sc, PIN2DRIVE_REG(pin), tmpr); 576 577 if ((flags & (GPIO_PIN_OUTPUT | GPIO_PIN_INOUT))) { 578 /* Configure pullup resistor or gate keeper. */ 579 if (flags & GPIO_PIN_PULLUP) 580 PINCTRL_WR(sc, PIN2PULL_SET_REG(pin), 581 PIN2PULL_MASK(pin)); 582 else 583 PINCTRL_WR(sc, PIN2PULL_CLR_REG(pin), 584 PIN2PULL_MASK(pin)); 585 586 /* Set initial pin value to logic zero. */ 587 PINCTRL_WR(sc, PIN2DOUT_CLR_REG(pin), PIN2DOUT_MASK(pin)); 588 589 /* Enable pin output. */ 590 PINCTRL_WR(sc, PIN2DOE_SET_REG(pin), PIN2DOE_MASK(pin)); 591 } 592 593 if (flags & GPIO_PIN_INPUT) { 594 /* Disable pin output. */ 595 PINCTRL_WR(sc, PIN2DOE_CLR_REG(pin), PIN2DOE_MASK(pin)); 596 597 /* Configure pullup resistor or gate keeper. */ 598 if (flags & GPIO_PIN_PULLUP) 599 PINCTRL_WR(sc, PIN2PULL_SET_REG(pin), 600 PIN2PULL_MASK(pin)); 601 else 602 PINCTRL_WR(sc, PIN2PULL_CLR_REG(pin), 603 PIN2PULL_MASK(pin)); 604 } 605 606 return; 607} 608