1/* $Id: imx23_digctlreg.h,v 1.2 2013/10/07 17:36:40 matt Exp $ */ 2 3/* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _ARM_IMX_IMX23_DIGCTLREG_H_ 33#define _ARM_IMX_IMX23_DIGCTLREG_H_ 34 35#include <sys/cdefs.h> 36 37#define HW_DIGCTL_BASE 0x8001C000 38#define HW_DIGCTL_SIZE 0x2000 39 40/* 41 * DIGCTL Control Register. 42 */ 43#define HW_DIGCTL_CTRL 0x000 44#define HW_DIGCTL_CTRL_SET 0x004 45#define HW_DIGCTL_CTRL_CLR 0x008 46#define HW_DIGCTL_CTRL_TOG 0x00C 47 48#define HW_DIGCTL_CTRL_RSVD3 __BIT(31) 49#define HW_DIGCTL_CTRL_XTAL24M_GATE __BIT(30) 50#define HW_DIGCTL_CTRL_TRAP_IRQ __BIT(29) 51#define HW_DIGCTL_CTRL_RSVD2 __BITS(28, 27) 52#define HW_DIGCTL_CTRL_CACHE_BIST_TMODE __BIT(26) 53#define HW_DIGCTL_CTRL_LCD_BIST_CLKEN __BIT(25) 54#define HW_DIGCTL_CTRL_LCD_BIST_START __BIT(24) 55#define HW_DIGCTL_CTRL_DCP_BIST_CLKEN __BIT(23) 56#define HW_DIGCTL_CTRL_DCP_BIST_START __BIT(22) 57#define HW_DIGCTL_CTRL_ARM_BIST_CLKEN __BIT(21) 58#define HW_DIGCTL_CTRL_USB_TESTMODE __BIT(20) 59#define HW_DIGCTL_CTRL_ANALOG_TESTMODE __BIT(19) 60#define HW_DIGCTL_CTRL_DIGITAL_TESTMODE __BIT(18) 61#define HW_DIGCTL_CTRL_ARM_BIST_START __BIT(17) 62#define HW_DIGCTL_CTRL_UART_LOOPBACK __BIT(16) 63#define HW_DIGCTL_CTRL_SAIF_LOOPBACK __BIT(15) 64#define HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL __BITS(14, 13) 65#define HW_DIGCTL_CTRL_SAIF_CLKMST_SEL __BIT(12) 66#define HW_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL __BIT(11) 67#define HW_DIGCTL_CTRL_RSVD1 __BIT(10) 68#define HW_DIGCTL_CTRL_SY_ENDIAN __BIT(9) 69#define HW_DIGCTL_CTRL_SY_SFTRST __BIT(8) 70#define HW_DIGCTL_CTRL_SY_CLKGATE __BIT(7) 71#define HW_DIGCTL_CTRL_USE_SERIAL_JTAG __BIT(6) 72#define HW_DIGCTL_CTRL_TRAP_IN_RANGE __BIT(5) 73#define HW_DIGCTL_CTRL_TRAP_ENABLE __BIT(4) 74#define HW_DIGCTL_CTRL_DEBUG_DISABLE __BIT(3) 75#define HW_DIGCTL_CTRL_USB_CLKGATE __BIT(2) 76#define HW_DIGCTL_CTRL_JTAG_SHIELD __BIT(1) 77#define HW_DIGCTL_CTRL_LATCH_ENTROPY __BIT(0) 78 79/* 80 * DIGCTL Status Register. 81 */ 82#define HW_DIGCTL_STATUS 0x010 83#define HW_DIGCTL_STATUS_SET 0x014 84#define HW_DIGCTL_STATUS_CLR 0x018 85#define HW_DIGCTL_STATUS_TOG 0x01C 86 87#define HW_DIGCTL_STATUS_USB_HS_PRESENT __BIT(31) 88#define HW_DIGCTL_STATUS_USB_OTG_PRESENT __BIT(30) 89#define HW_DIGCTL_STATUS_USB_HOST_PRESENT __BIT(29) 90#define HW_DIGCTL_STATUS_USB_DEVICE_PRESENT __BIT(28) 91#define HW_DIGCTL_STATUS_RSVD2 __BITS(27, 11) 92#define HW_DIGCTL_STATUS_DCP_BIST_FAIL __BIT(10) 93#define HW_DIGCTL_STATUS_DCP_BIST_PASS __BIT(9) 94#define HW_DIGCTL_STATUS_DCP_BIST_DONE __BIT(8) 95#define HW_DIGCTL_STATUS_LCD_BIST_FAIL __BIT(7) 96#define HW_DIGCTL_STATUS_LCD_BIST_PASS __BIT(6) 97#define HW_DIGCTL_STATUS_LCD_BIST_DONE __BIT(5) 98#define HW_DIGCTL_STATUS_JTAG_IN_USE __BIT(4) 99#define HW_DIGCTL_STATUS_PACKAGE_TYPE __BITS(3, 1) 100#define HW_DIGCTL_STATUS_WRITTEN __BIT(0) 101 102/* 103 * Free-Running HCLK Counter Register. 104 */ 105#define HW_DIGCTL_HCLKCOUNT 0x020 106#define HW_DIGCTL_HCLKCOUNT_SET 0x024 107#define HW_DIGCTL_HCLKCOUNT_CLR 0x028 108#define HW_DIGCTL_HCLKCOUNT_TOG 0x02C 109 110#define HW_DIGCTL_HCLKCOUNT_COUNT __BITS(31, 0) 111 112/* 113 * On-Chip RAM Control Register. 114 */ 115#define HW_DIGCTL_RAMCTRL 0x030 116#define HW_DIGCTL_RAMCTRL_SET 0x034 117#define HW_DIGCTL_RAMCTRL_CLR 0x038 118#define HW_DIGCTL_RAMCTRL_TOG 0x03C 119 120#define HW_DIGCTL_RAMCTRL_RSVD1 __BITS(31, 12) 121#define HW_DIGCTL_RAMCTRL_SPEED_SELECT __BITS(11, 8) 122#define HW_DIGCTL_RAMCTRL_RSVD0 __BITS(7, 1) 123#define HW_DIGCTL_RAMCTRL_RAM_REPAIR_EN __BIT(0) 124 125/* 126 * On-Chip RAM Repair Address Register. 127 */ 128#define HW_DIGCTL_RAMREPAIR 0x040 129#define HW_DIGCTL_RAMREPAIR_SET 0x044 130#define HW_DIGCTL_RAMREPAIR_CLR 0x048 131#define HW_DIGCTL_RAMREPAIR_TOG 0x04C 132 133#define HW_DIGCTL_RAMREPAIR_RSVD1 __BITS(31, 16) 134#define HW_DIGCTL_RAMREPAIR_ADDR __BITS(15, 0) 135 136/* 137 * On-Chip ROM Control Register. 138 */ 139#define HW_DIGCTL_ROMCTRL 0x050 140#define HW_DIGCTL_ROMCTRL_SET 0x054 141#define HW_DIGCTL_ROMCTRL_CLR 0x058 142#define HW_DIGCTL_ROMCTRL_TOG 0x05C 143 144#define HW_DIGCTL_ROMCTRL_RSVD0 __BITS(31, 4) 145#define HW_DIGCTL_ROMCTRL_RD_MARGIN __BITS(3, 0) 146 147/* 148 * Software Write-Once Register. 149 */ 150#define HW_DIGCTL_WRITEONCE 0x060 151 152#define HW_DIGCTL_WRITEONCE_BITS __BITS(31, 0) 153 154/* 155 * Entropy Register. 156 */ 157#define HW_DIGCTL_ENTROPY 0x090 158 159#define HW_DIGCTL_ENTROPY_VALUE __BITS(31, 0) 160 161/* 162 * Entropy Latched Register. 163 */ 164#define HW_DIGCTL_ENTROPY_LATCHED 0x0A0 165 166#define HW_DIGCTL_ENTROPY_VALUE __BITS(31, 0) 167 168/* 169 * SJTAG Debug Register. 170 */ 171#define HW_DIGCTL_SJTAGDBG 0x0B0 172#define HW_DIGCTL_SJTAGDBG_SET 0x0B4 173#define HW_DIGCTL_SJTAGDBG_CLR 0x0B8 174#define HW_DIGCTL_SJTAGDBG_TOG 0x0BC 175 176#define HW_DIGCTL_SJTAGDBG_RSVD2 __BITS(31, 27) 177#define HW_DIGCTL_SJTAGDBG_SJTAG_STATE __BITS(26, 16) 178#define HW_DIGCTL_SJTAGDBG_RSVD1 __BITS(15, 11) 179#define HW_DIGCTL_SJTAGDBG_SJTAG_TDO __BIT(10) 180#define HW_DIGCTL_SJTAGDBG_SJTAG_TDI __BIT(9) 181#define HW_DIGCTL_SJTAGDBG_SJTAG_MODE __BIT(8) 182#define HW_DIGCTL_SJTAGDBG_DELAYED_ACTIVE __BITS(7, 4) 183#define HW_DIGCTL_SJTAGDBG_ACTIVE __BIT(3) 184#define HW_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE __BIT(2) 185#define HW_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA __BIT(1) 186#define HW_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE __BIT(0) 187 188/* 189 * Digital Control Microseconds Counter Register. 190 */ 191#define HW_DIGCTL_MICROSECONDS 0x0C0 192#define HW_DIGCTL_MICROSECONDS_SET 0x0C4 193#define HW_DIGCTL_MICROSECONDS_CLR 0x0C8 194#define HW_DIGCTL_MICROSECONDS_TOG 0x0CC 195 196#define HW_DIGCTL_MICROSECONDS_VALUE __BITS(31, 0) 197 198/* 199 * Digital Control Debug Read Test Register. 200 */ 201#define HW_DIGCTL_DBGRD 0x0D0 202 203#define HW_DIGCTL_DBGRD_COMPLEMENT __BITS(31, 0) 204 205/* 206 * Digital Control Debug Register. 207 */ 208#define HW_DIGCTL_DBG 0x0E0 209 210#define HW_DIGCTL_DBG_VALUE __BITS(31, 0) 211 212/* 213 * SRAM BIST Control and Status Register. 214 */ 215#define HW_DIGCTL_OCRAM_BIST_CSR 0x0F0 216#define HW_DIGCTL_OCRAM_BIST_CSR_SET 0x0F4 217#define HW_DIGCTL_OCRAM_BIST_CSR_CLR 0x0F8 218#define HW_DIGCTL_OCRAM_BIST_CSR_TOG 0x0FC 219 220#define HW_DIGCTL_OCRAM_BIST_CSR_RSVD1 __BITS(31, 11) 221#define HW_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE __BIT(10) 222#define HW_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE __BIT(9) 223#define HW_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN __BIT(8) 224#define HW_DIGCTL_OCRAM_BIST_CSR_RSVD0 __BITS(7, 4) 225#define HW_DIGCTL_OCRAM_BIST_CSR_FAIL __BIT(3) 226#define HW_DIGCTL_OCRAM_BIST_CSR_PASS __BIT(2) 227#define HW_DIGCTL_OCRAM_BIST_CSR_DONE __BIT(1) 228#define HW_DIGCTL_OCRAM_BIST_CSR_START __BIT(0) 229 230/* 231 * SRAM Status Register 0. 232 */ 233#define HW_DIGCTL_OCRAM_STATUS0 0x110 234#define HW_DIGCTL_OCRAM_STATUS0_SET 0x114 235#define HW_DIGCTL_OCRAM_STATUS0_CLR 0x118 236#define HW_DIGCTL_OCRAM_STATUS0_TOG 0x11C 237 238#define HW_DIGCTL_OCRAM_STATUS0_FAILDATA00 __BITS(31, 0) 239 240/* 241 * SRAM Status Register 1. 242 */ 243#define HW_DIGCTL_OCRAM_STATUS1 0x120 244#define HW_DIGCTL_OCRAM_STATUS1_SET 0x124 245#define HW_DIGCTL_OCRAM_STATUS1_CLR 0x128 246#define HW_DIGCTL_OCRAM_STATUS1_TOG 0x12C 247 248#define HW_DIGCTL_OCRAM_STATUS1_FAILDATA01 __BITS(31, 0) 249 250/* 251 * SRAM Status Register 2. 252 */ 253#define HW_DIGCTL_OCRAM_STATUS2 0x130 254#define HW_DIGCTL_OCRAM_STATUS2_SET 0x134 255#define HW_DIGCTL_OCRAM_STATUS2_CLR 0x138 256#define HW_DIGCTL_OCRAM_STATUS2_TOG 0x13C 257 258#define HW_DIGCTL_OCRAM_STATUS2_FAILDATA10 __BITS(31, 0) 259 260/* 261 * SRAM Status Register 3. 262 */ 263#define HW_DIGCTL_OCRAM_STATUS3 0x140 264#define HW_DIGCTL_OCRAM_STATUS3_SET 0x144 265#define HW_DIGCTL_OCRAM_STATUS3_CLR 0x148 266#define HW_DIGCTL_OCRAM_STATUS3_TOG 0x14C 267 268#define HW_DIGCTL_OCRAM_STATUS3_FAILDATA20 __BITS(31, 0) 269 270/* 271 * SRAM Status Register 4. 272 */ 273#define HW_DIGCTL_OCRAM_STATUS4 0x150 274#define HW_DIGCTL_OCRAM_STATUS4_SET 0x154 275#define HW_DIGCTL_OCRAM_STATUS4_CLR 0x158 276#define HW_DIGCTL_OCRAM_STATUS4_TOG 0x15C 277 278#define HW_DIGCTL_OCRAM_STATUS4_FAILDATA20 __BITS(31, 0) 279 280/* 281 * SRAM Status Register 5. 282 */ 283#define HW_DIGCTL_OCRAM_STATUS5 0x160 284#define HW_DIGCTL_OCRAM_STATUS5_SET 0x164 285#define HW_DIGCTL_OCRAM_STATUS5_CLR 0x168 286#define HW_DIGCTL_OCRAM_STATUS5_TOG 0x16C 287 288#define HW_DIGCTL_OCRAM_STATUS5_FAILDATA21 __BITS(31, 0) 289 290/* 291 * SRAM Status Register 6. 292 */ 293#define HW_DIGCTL_OCRAM_STATUS6 0x170 294#define HW_DIGCTL_OCRAM_STATUS6_SET 0x174 295#define HW_DIGCTL_OCRAM_STATUS6_CLR 0x178 296#define HW_DIGCTL_OCRAM_STATUS6_TOG 0x17C 297 298#define HW_DIGCTL_OCRAM_STATUS6_FAILDATA30 __BITS(31, 0) 299 300/* 301 * SRAM Status Register 7. 302 */ 303#define HW_DIGCTL_OCRAM_STATUS7 0x180 304#define HW_DIGCTL_OCRAM_STATUS7_SET 0x184 305#define HW_DIGCTL_OCRAM_STATUS7_CLR 0x188 306#define HW_DIGCTL_OCRAM_STATUS7_TOG 0x18C 307 308#define HW_DIGCTL_OCRAM_STATUS7_FAILDATA31 __BITS(31, 0) 309 310/* 311 * SRAM Status Register 8. 312 */ 313#define HW_DIGCTL_OCRAM_STATUS8 0x190 314#define HW_DIGCTL_OCRAM_STATUS8_SET 0x194 315#define HW_DIGCTL_OCRAM_STATUS8_CLR 0x198 316#define HW_DIGCTL_OCRAM_STATUS8_TOG 0x19C 317 318#define HW_DIGCTL_OCRAM_STATUS8_RSVD3 __BITS(31, 29) 319#define HW_DIGCTL_OCRAM_STATUS8_FAILADDR01 __BITS(28, 16) 320#define HW_DIGCTL_OCRAM_STATUS8_RSVD2 __BITS(15, 13) 321#define HW_DIGCTL_OCRAM_STATUS8_FAILADDR00 __BITS(12, 0) 322 323/* 324 * SRAM Status Register 9. 325 */ 326#define HW_DIGCTL_OCRAM_STATUS9 0x1A0 327#define HW_DIGCTL_OCRAM_STATUS9_SET 0x1A4 328#define HW_DIGCTL_OCRAM_STATUS9_CLR 0x1A8 329#define HW_DIGCTL_OCRAM_STATUS9_TOG 0x1AC 330 331#define HW_DIGCTL_OCRAM_STATUS9_RSVD3 __BITS(31, 29) 332#define HW_DIGCTL_OCRAM_STATUS9_FAILADDR11 __BITS(28, 16) 333#define HW_DIGCTL_OCRAM_STATUS9_RSVD2 __BITS(15, 13) 334#define HW_DIGCTL_OCRAM_STATUS9_FAILADDR10 __BITS(12, 0) 335 336/* 337 * SRAM Status Register 10. 338 */ 339#define HW_DIGCTL_OCRAM_STATUS10 0x1B0 340#define HW_DIGCTL_OCRAM_STATUS10_SET 0x1B4 341#define HW_DIGCTL_OCRAM_STATUS10_CLR 0x1B8 342#define HW_DIGCTL_OCRAM_STATUS10_TOG 0x1BC 343 344#define HW_DIGCTL_OCRAM_STATUS10_RSVD3 __BITS(31, 29) 345#define HW_DIGCTL_OCRAM_STATUS10_FAILADDR21 __BITS(28, 16) 346#define HW_DIGCTL_OCRAM_STATUS10_RSVD2 __BITS(15, 13) 347#define HW_DIGCTL_OCRAM_STATUS10_FAILADDR20 __BITS(12, 0) 348 349/* 350 * SRAM Status Register 11. 351 */ 352#define HW_DIGCTL_OCRAM_STATUS11 0x1C0 353#define HW_DIGCTL_OCRAM_STATUS11_SET 0x1C4 354#define HW_DIGCTL_OCRAM_STATUS11_CLR 0x1C8 355#define HW_DIGCTL_OCRAM_STATUS11_TOG 0x1CC 356 357#define HW_DIGCTL_OCRAM_STATUS11_RSVD3 __BITS(31, 29) 358#define HW_DIGCTL_OCRAM_STATUS11_FAILADDR31 __BITS(28, 16) 359#define HW_DIGCTL_OCRAM_STATUS11_RSVD2 __BITS(15, 13) 360#define HW_DIGCTL_OCRAM_STATUS11_FAILADDR30 __BITS(12, 0) 361 362/* 363 * SRAM Status Register 12. 364 */ 365#define HW_DIGCTL_OCRAM_STATUS12 0x1D0 366#define HW_DIGCTL_OCRAM_STATUS12_SET 0x1D4 367#define HW_DIGCTL_OCRAM_STATUS12_CLR 0x1D8 368#define HW_DIGCTL_OCRAM_STATUS12_TOG 0x1DC 369 370#define HW_DIGCTL_OCRAM_STATUS12_RSVD3 __BITS(31, 28) 371#define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE11 __BITS(27, 24) 372#define HW_DIGCTL_OCRAM_STATUS12_RSVD2 __BITS(23, 20) 373#define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE10 __BITS(19, 16) 374#define HW_DIGCTL_OCRAM_STATUS12_RSVD1 __BITS(15, 12) 375#define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE01 __BITS(11, 8) 376#define HW_DIGCTL_OCRAM_STATUS12_RSVD0 __BITS(7, 4) 377#define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE00 __BITS(3, 0) 378 379/* 380 * SRAM Status Register 13. 381 */ 382#define HW_DIGCTL_OCRAM_STATUS13 0x1E0 383#define HW_DIGCTL_OCRAM_STATUS13_SET 0x1E4 384#define HW_DIGCTL_OCRAM_STATUS13_CLR 0x1E8 385#define HW_DIGCTL_OCRAM_STATUS13_TOG 0x1EC 386 387#define HW_DIGCTL_OCRAM_STATUS13_RSVD3 __BITS(31, 28) 388#define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE31 __BITS(27, 24) 389#define HW_DIGCTL_OCRAM_STATUS13_RSVD2 __BITS(23, 20) 390#define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE30 __BITS(19, 16) 391#define HW_DIGCTL_OCRAM_STATUS13_RSVD1 __BITS(15, 12) 392#define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE21 __BITS(11, 8) 393#define HW_DIGCTL_OCRAM_STATUS13_RSVD0 __BITS(7, 4) 394#define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE20 __BITS(3, 0) 395 396/* 397 * Digital Control Scratch Register 0. 398 */ 399#define HW_DIGCTL_SCRATCH0 0x290 400 401#define HW_DIGCTL_SCRATCH0_PTR __BITS(31, 0) 402 403/* 404 * Digital Control Scratch Register 1. 405 */ 406#define HW_DIGCTL_SCRATCH1 0x2A0 407 408#define HW_DIGCTL_SCRATCH1_PTR __BITS(31, 0) 409 410/* 411 * Digital Control ARM Cache Register. 412 */ 413#define HW_DIGCTL_ARMCACHE 0x2B0 414 415#define HW_DIGCTL_ARMCACHE_RSVD4 __BITS(31, 18) 416#define HW_DIGCTL_ARMCACHE_VALID_SS __BITS(17, 16) 417#define HW_DIGCTL_ARMCACHE_RSVD3 __BITS(15, 14) 418#define HW_DIGCTL_ARMCACHE_DRTY_SS __BITS(13, 12) 419#define HW_DIGCTL_ARMCACHE_RSVD2 __BITS(11, 10) 420#define HW_DIGCTL_ARMCACHE_CACHE_SS __BITS(9, 8) 421#define HW_DIGCTL_ARMCACHE_RSVD1 __BITS(7, 6) 422#define HW_DIGCTL_ARMCACHE_DTAG_SS __BITS(5, 4) 423#define HW_DIGCTL_ARMCACHE_RSVD0 __BITS(3, 2) 424#define HW_DIGCTL_ARMCACHE_ITAG_SS __BITS(1, 0) 425 426/* 427 * Debug Trap Range Low Address. 428 */ 429#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW 0x2C0 430 431#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR __BITS(31, 0) 432 433/* 434 * Debug Trap Range High Address. 435 */ 436#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH 0x2D0 437 438#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR __BITS(31, 0) 439 440/* 441 * Freescale Copyright Identifier Register. 442 */ 443#define HW_DIGCTL_SGTL 0x300 444 445#define HW_DIGCTL_SGTL_COPYRIGHT __BITS(31, 0) 446 447/* 448 * Digital Control Chip Revision Register. 449 */ 450#define HW_DIGCTL_CHIPID 0x310 451 452#define HW_DIGCTL_CHIPID_PRODUCT_CODE __BITS(31, 16) 453#define HW_DIGCTL_CHIPID_RSVD0 __BITS(16, 8) 454#define HW_DIGCTL_CHIPID_REVISION __BITS(7, 0) 455 456/* 457 * AHB Statistics Control Register. 458 */ 459#define HW_DIGCTL_AHB_STATS_SELECT 0x330 460 461#define HW_DIGCTL_AHB_STATS_SELECT_RSVD3 __BITS(31, 28) 462#define HW_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT __BITS(27, 24) 463#define HW_DIGCTL_AHB_STATS_SELECT_RSVD2 __BITS(23, 20) 464#define HW_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT __BITS(19, 16) 465#define HW_DIGCTL_AHB_STATS_SELECT_RSVD1 __BITS(15, 12) 466#define HW_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT __BITS(11, 8) 467#define HW_DIGCTL_AHB_STATS_SELECT_RSVD0 __BITS(7, 4) 468#define HW_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT __BITS(3, 0) 469 470/* 471 * AHB Layer 0 Transfer Count Register. 472 */ 473#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES 0x340 474 475#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0) 476 477/* 478 * AHB Layer 0 Performance Metric for Stalled Bus Cycles Register. 479 */ 480#define HW_DIGCTL_L0_AHB_DATA_STALLED 0x350 481 482#define HW_DIGCTL_L0_AHB_DATA_STALLED_COUNT __BITS(31, 0) 483 484/* 485 * AHB Layer 0 Performance Metric for Valid Bus Cycles Register. 486 */ 487#define HW_DIGCTL_L0_AHB_DATA_CYCLES 0x360 488 489#define HW_DIGCTL_L0_AHB_DATA_CYCLES_COUNT __BITS(31, 0) 490 491/* 492 * AHB Layer 1 Transfer Count Register. 493 */ 494#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES 0x370 495 496#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0) 497 498/* 499 * AHB Layer 1 Performance Metric for Stalled Bus Cycles Register. 500 */ 501#define HW_DIGCTL_L1_AHB_DATA_STALLED 0x380 502 503#define HW_DIGCTL_L1_AHB_DATA_STALLED_COUNT __BITS(31, 0) 504 505/* 506 * AHB Layer 1 Performance Metric for Stalled Bus Cycles Register. 507 */ 508#define HW_DIGCTL_L1_AHB_DATA_STALLED 0x380 509 510#define HW_DIGCTL_L1_AHB_DATA_STALLED_COUNT __BITS(31, 0) 511 512/* 513 * AHB Layer 1 Performance Metric for Valid Bus Cycles Register. 514 */ 515#define HW_DIGCTL_L1_AHB_DATA_CYCLES 0x390 516 517#define HW_DIGCTL_L1_AHB_DATA_CYCLES_COUNT __BITS(31, 0) 518 519/* 520 * AHB Layer 2 Transfer Count Register. 521 */ 522#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES 0x3A0 523 524#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0) 525 526/* 527 * AHB Layer 2 Performance Metric for Stalled Bus Cycles Register. 528 */ 529#define HW_DIGCTL_L2_AHB_DATA_STALLED 0x3B0 530 531#define HW_DIGCTL_L2_AHB_DATA_STALLED_COUNT __BITS(31, 0) 532 533/* 534 * AHB Layer 2 Performance Metric for Valid Bus Cycles Register. 535 */ 536#define HW_DIGCTL_L2_AHB_DATA_CYCLES 0x3C0 537 538#define HW_DIGCTL_L2_AHB_DATA_CYCLES_COUNT __BITS(31, 0) 539 540/* 541 * AHB Layer 3 Transfer Count Register. 542 */ 543#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES 0x3D0 544 545#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0) 546 547/* 548 * AHB Layer 3 Performance Metric for Stalled Bus Cycles Register. 549 */ 550#define HW_DIGCTL_L3_AHB_DATA_STALLED 0x3E0 551 552#define HW_DIGCTL_L3_AHB_DATA_STALLED_COUNT __BITS(31, 0) 553 554/* 555 * AHB Layer 3 Performance Metric for Valid Bus Cycles Register. 556 */ 557#define HW_DIGCTL_L3_AHB_DATA_CYCLES 0x3F0 558 559#define HW_DIGCTL_L3_AHB_DATA_CYCLES_COUNT __BITS(31, 0) 560 561/* 562 * EMI CLK/CLKN Delay Adjustment Register. 563 */ 564#define HW_DIGCTL_EMICLK_DELAY 0x500 565 566#define HW_DIGCTL_EMICLK_DELAY_RSVD0 __BITS(31, 5) 567#define HW_DIGCTL_EMICLK_DELAY_NUM_TAPS __BITS(4, 0) 568 569#endif /* !_ARM_IMX_IMX23_DIGCTLREG_H_ */ 570