1/* $Id: imx23_clkctrlreg.h,v 1.2 2013/10/07 17:36:40 matt Exp $ */ 2 3/* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _ARM_IMX_IMX23_CLKCTRLREG_H_ 33#define _ARM_IMX_IMX23_CLKCTRLREG_H_ 34 35#include <sys/cdefs.h> 36 37#define HW_CLKCTRL_BASE 0x80040000 38#define HW_CLKCTRL_SIZE 0x2000 39 40/* 41 * PLL Control Register 0. 42 */ 43#define HW_CLKCTRL_PLLCTRL0 0x000 44#define HW_CLKCTRL_PLLCTRL0_SET 0x004 45#define HW_CLKCTRL_PLLCTRL0_CLR 0x008 46#define HW_CLKCTRL_PLLCTRL0_TOG 0x00C 47 48#define HW_CLKCTRL_PLLCTRL0_RSRVD6 __BITS(31, 30) 49#define HW_CLKCTRL_PLLCTRL0_LFR_SEL __BITS(29, 28) 50#define HW_CLKCTRL_PLLCTRL0_RSRVD5 __BITS(27, 26) 51#define HW_CLKCTRL_PLLCTRL0_CP_SEL __BITS(25, 24) 52#define HW_CLKCTRL_PLLCTRL0_RSRVD4 __BITS(23, 22) 53#define HW_CLKCTRL_PLLCTRL0_DIV_SEL __BITS(21, 20) 54#define HW_CLKCTRL_PLLCTRL0_RSRVD3 __BIT(19) 55#define HW_CLKCTRL_PLLCTRL0_EN_USB_CLKS __BIT(18) 56#define HW_CLKCTRL_PLLCTRL0_RSRVD2 __BIT(17) 57#define HW_CLKCTRL_PLLCTRL0_POWER __BIT(16) 58#define HW_CLKCTRL_PLLCTRL0_RSRVD1 __BITS(15, 0) 59 60/* 61 * PLL Control Register 1. 62 */ 63#define HW_CLKCTRL_PLLCTRL1 0x010 64 65#define HW_CLKCTRL_PLLCTRL1_LOCK __BIT(31) 66#define HW_CLKCTRL_PLLCTRL1_FORCE_LOCK __BIT(30) 67#define HW_CLKCTRL_PLLCTRL1_RSRVD1 __BITS(29, 16) 68#define HW_CLKCTRL_PLLCTRL1_LOCK_COUNT __BITS(15, 0) 69 70/* 71 * CPU Clock Control Register. 72 */ 73#define HW_CLKCTRL_CPU 0x020 74#define HW_CLKCTRL_CPU_SET 0x024 75#define HW_CLKCTRL_CPU_CLR 0x028 76#define HW_CLKCTRL_CPU_TOG 0x02c 77 78#define HW_CLKCTRL_CPU_RSVD6 __BITS(31, 30) 79#define HW_CLKCTRL_CPU_BUSY_REF_XTAL __BIT(29) 80#define HW_CLKCTRL_CPU_BUSY_REF_CPU __BIT(28) 81#define HW_CLKCTRL_CPU_RSVD5 __BIT(27) 82#define HW_CLKCTRL_CPU_DIV_XTAL_FRAC_EN __BIT(26) 83#define HW_CLKCTRL_CPU_DIV_XTAL __BITS(25, 16) 84#define HW_CLKCTRL_CPU_RSVD4 __BITS(15, 13) 85#define HW_CLKCTRL_CPU_INTERRUPT_WAIT __BIT(12) 86#define HW_CLKCTRL_CPU_RSVD3 __BIT(11) 87#define HW_CLKCTRL_CPU_RSVD2 __BIT(10) 88#define HW_CLKCTRL_CPU_RSVD1 __BITS(9, 6) 89#define HW_CLKCTRL_CPU_DIV_CPU __BITS(5, 0) 90 91/* 92 * AHB, APBH Bus Clock Control Register. 93 */ 94#define HW_CLKCTRL_HBUS 0x030 95#define HW_CLKCTRL_HBUS_SET 0x034 96#define HW_CLKCTRL_HBUS_CLR 0x038 97#define HW_CLKCTRL_HBUS_TOG 0x03c 98 99#define HW_CLKCTRL_HBUS_RSRVD4 __BITS(31, 30) 100#define HW_CLKCTRL_HBUS_BUSY __BIT(29) 101#define HW_CLKCTRL_HBUS_DCP_AS_ENABLE __BIT(28) 102#define HW_CLKCTRL_HBUS_PXP_AS_ENABLE __BIT(27) 103#define HW_CLKCTRL_HBUS_APBHDMA_AS_ENABLE __BIT(26) 104#define HW_CLKCTRL_HBUS_APBXDMA_AS_ENABLE __BIT(25) 105#define HW_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE __BIT(24) 106#define HW_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE __BIT(23) 107#define HW_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE __BIT(22) 108#define HW_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE __BIT(21) 109#define HW_CLKCTRL_HBUS_AUTO_SLOW_MODE __BIT(20) 110#define HW_CLKCTRL_HBUS_RSRVD2 __BIT(19) 111#define HW_CLKCTRL_HBUS_SLOW_DIV __BITS(18, 16) 112#define HW_CLKCTRL_HBUS_RSRVD1 __BITS(15, 6) 113#define HW_CLKCTRL_HBUS_DIV_FRAC_EN __BIT(5) 114#define HW_CLKCTRL_HBUS_DIV __BITS(4, 0) 115 116/* 117 * APBX Clock Control Register. 118 */ 119#define HW_CLKCTRL_XBUS 0x040 120 121#define HW_CLKCTRL_XBUS_BUSY __BIT(31) 122#define HW_CLKCTRL_XBUS_RSVD2 __BITS(30, 11) 123#define HW_CLKCTRL_XBUS_RSVD1 __BIT(10) 124#define HW_CLKCTRL_XBUS_DIV __BITS(9, 0) 125 126/* 127 * XTAL Clock Control Register. 128 */ 129#define HW_CLKCTRL_XTAL 0x050 130#define HW_CLKCTRL_XTAL_SET 0x054 131#define HW_CLKCTRL_XTAL_CLR 0x058 132#define HW_CLKCTRL_XTAL_TOG 0x05C 133 134#define HW_CLKCTRL_XTAL_UART_CLK_GATE __BIT(31) 135#define HW_CLKCTRL_XTAL_FILT_CLK24M_GATE __BIT(30) 136#define HW_CLKCTRL_XTAL_PWM_CLK24M_GATE __BIT(29) 137#define HW_CLKCTRL_XTAL_DRI_CLK24M_GATE __BIT(28) 138#define HW_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE __BIT(27) 139#define HW_CLKCTRL_XTAL_TIMROT_CLK32K_GATE __BIT(26) 140#define HW_CLKCTRL_XTAL_RSRVD1 __BITS(25, 2) 141#define HW_CLKCTRL_XTAL_DIV_UART __BITS(1, 0) 142 143/* 144 * PIX (LCDIF) Clock Control Register. 145 */ 146#define HW_CLKCTRL_PIX 0x060 147 148#define HW_CLKCTRL_PIX_CLKGATE __BIT(31) 149#define HW_CLKCTRL_PIX_RSRVD2 __BIT(30) 150#define HW_CLKCTRL_PIX_BUSY __BIT(29) 151#define HW_CLKCTRL_PIX_RSRVD1 __BITS(28, 13) 152#define HW_CLKCTRL_PIX_DIV_FRAC_EN __BIT(12) 153#define HW_CLKCTRL_PIX_DIV __BITS(11, 0) 154 155/* 156 * Synchronous Serial Port Clock Control Register. 157 */ 158#define HW_CLKCTRL_SSP 0x070 159 160#define HW_CLKCTRL_SSP_CLKGATE __BIT(31) 161#define HW_CLKCTRL_SSP_RSVD3 __BIT(30) 162#define HW_CLKCTRL_SSP_BUSY __BIT(29) 163#define HW_CLKCTRL_SSP_RSVD2 __BITS(28, 10) 164#define HW_CLKCTRL_SSP_RSVD1 __BIT(9) 165#define HW_CLKCTRL_SSP_DIV __BITS(8, 0) 166 167/* 168 * General-Purpose Media Interface Clock Control Register. 169 */ 170#define HW_CLKCTRL_GPMI 0x080 171 172#define HW_CLKCTRL_GPMI_CLKGATE __BIT(31) 173#define HW_CLKCTRL_GPMI_RSVD3 __BIT(30) 174#define HW_CLKCTRL_GPMI_BUSY __BIT(29) 175#define HW_CLKCTRL_GPMI_RSVD2 __BITS(28, 11) 176#define HW_CLKCTRL_GPMI_RSVD1 __BIT(10) 177#define HW_CLKCTRL_GPMI_DIV __BIT(9, 0) 178 179/* 180 * SPDIF Clock Control Register. 181 */ 182#define HW_CLKCTRL_SPDIF 0x090 183 184#define HW_CLKCTRL_SPDIF_CLKGATE __BIT(31) 185#define HW_CLKCTRL_SPDIF_RSRVD __BITS(30, 0) 186 187/* 188 * EMI Clock Control Register. 189 */ 190#define HW_CLKCTRL_EMI 0x0a0 191 192#define HW_CLKCTRL_EMI_CLKGATE __BIT(31) 193#define HW_CLKCTRL_EMI_SYNC_MODE_EN __BIT(30) 194#define HW_CLKCTRL_EMI_BUSY_REF_XTAL __BIT(29) 195#define HW_CLKCTRL_EMI_BUSY_REF_EMI __BIT(28) 196#define HW_CLKCTRL_EMI_BUSY_REF_CPU __BIT(27) 197#define HW_CLKCTRL_EMI_BUSY_SYNC_MODE __BIT(26) 198#define HW_CLKCTRL_EMI_RSVD5 __BITS(25, 18) 199#define HW_CLKCTRL_EMI_RSVD4 __BIT(17) 200#define HW_CLKCTRL_EMI_RSVD3 __BIT(16) 201#define HW_CLKCTRL_EMI_RSVD2 __BITS(15, 12) 202#define HW_CLKCTRL_EMI_DIV_XTAL __BITS(11, 8) 203#define HW_CLKCTRL_EMI_RSVD1 __BITS(7, 6) 204#define HW_CLKCTRL_EMI_DIV_EMI __BITS(5, 0) 205 206/* 207 * SAIF Clock Control Register. 208 */ 209#define HW_CLKCTRL_SAIF 0x0c0 210 211#define HW_CLKCTRL_SAIF_CLKGATE __BIT(31) 212#define HW_CLKCTRL_SAIF_RSRVD2 __BIT(30) 213#define HW_CLKCTRL_SAIF_BUSY __BIT(29) 214#define HW_CLKCTRL_SAIF_RSRVD1 __BITS(28, 17) 215#define HW_CLKCTRL_SAIF_DIV_FRAC_EN __BIT(16) 216#define HW_CLKCTRL_SAIF_DIV __BITS(15, 0) 217 218/* 219 * TV Encoder Clock Control Register. 220 */ 221#define HW_CLKCTRL_TV 0x0d0 222 223#define HW_CLKCTRL_TV_CLK_TV108M_GATE __BIT(31) 224#define HW_CLKCTRL_TV_CLK_TV_GATE __BIT(30) 225#define HW_CLKCTRL_TV_RSRVD __BITS(29, 0) 226 227/* 228 * ETM Clock Control Register. 229 */ 230#define HW_CLKCTRL_ETM 0x0e0 231 232#define HW_CLKCTRL_ETM_CLKGATE __BIT(31) 233#define HW_CLKCTRL_ETM_RSRVD2 __BIT(30) 234#define HW_CLKCTRL_ETM_BUSY __BIT(29) 235#define HW_CLKCTRL_ETM_RSRVD1 __BITS(28, 7) 236#define HW_CLKCTRL_ETM_DIV_FRAC_EN __BIT(6) 237#define HW_CLKCTRL_ETM_DIV __BITs(5, 0) 238 239/* 240 * Fractional Clock Control Register. 241 */ 242#define HW_CLKCTRL_FRAC 0x0f0 243#define HW_CLKCTRL_FRAC_SET 0x0f4 244#define HW_CLKCTRL_FRAC_CLR 0x0f8 245#define HW_CLKCTRL_FRAC_TOG 0x0fC 246 247#define HW_CLKCTRL_FRAC_CLKGATEIO __BIT(31) 248#define HW_CLKCTRL_FRAC_IO_STABLE __BIT(30) 249#define HW_CLKCTRL_FRAC_IOFRAC __BITS(29, 24) 250#define HW_CLKCTRL_FRAC_CLKGATEPIX __BIT(23) 251#define HW_CLKCTRL_FRAC_PIX_STABLE __BIT(22) 252#define HW_CLKCTRL_FRAC_PIXFRAC __BITS(21, 16) 253#define HW_CLKCTRL_FRAC_CLKGATEEMI __BIT(15) 254#define HW_CLKCTRL_FRAC_EMI_STABLE __BIT(14) 255#define HW_CLKCTRL_FRAC_EMIFRAC __BITS(13, 8) 256#define HW_CLKCTRL_FRAC_CLKGATECPU __BIT(7) 257#define HW_CLKCTRL_FRAC_CPU_STABLE __BIT(6) 258#define HW_CLKCTRL_FRAC_CPUFRAC __BITS(5, 0) 259 260/* 261 * Fractional Clock Control Register 1. 262 */ 263#define HW_CLKCTRL_FRAC1 0x100 264#define HW_CLKCTRL_FRAC1_SET 0x104 265#define HW_CLKCTRL_FRAC1_CLR 0x108 266#define HW_CLKCTRL_FRAC1_TOG 0x10C 267 268#define HW_CLKCTRL_FRAC1_CLKGATEVID __BIT(31) 269#define HW_CLKCTRL_FRAC1_VID_STABLE __BIT(30) 270#define HW_CLKCTRL_FRAC1_RSRVD1 __BITS(29, 0) 271 272/* 273 * Clock Frequency Sequence Control Register. 274 */ 275#define HW_CLKCTRL_CLKSEQ 0x110 276#define HW_CLKCTRL_CLKSEQ_SET 0x114 277#define HW_CLKCTRL_CLKSEQ_CLR 0x118 278#define HW_CLKCTRL_CLKSEQ_TOG 0x11c 279 280#define HW_CLKCTRL_CLKSEQ_RSRVD1 __BITS(31, 9) 281#define HW_CLKCTRL_CLKSEQ_BYPASS_ETM __BIT(8) 282#define HW_CLKCTRL_CLKSEQ_BYPASS_CPU __BIT(7) 283#define HW_CLKCTRL_CLKSEQ_BYPASS_EMI __BIT(6) 284#define HW_CLKCTRL_CLKSEQ_BYPASS_SSP __BIT(5) 285#define HW_CLKCTRL_CLKSEQ_BYPASS_GPMI __BIT(4) 286#define HW_CLKCTRL_CLKSEQ_BYPASS_IR __BIT(3) 287#define HW_CLKCTRL_CLKSEQ_RSRVD0 __BIT(2) 288#define HW_CLKCTRL_CLKSEQ_BYPASS_PIX __BIT(1) 289#define HW_CLKCTRL_CLKSEQ_BYPASS_SAIF __BIT(0) 290 291/* 292 * System Software Reset Register. 293 */ 294#define HW_CLKCTRL_RESET 0x120 295 296#define HW_CLKCTRL_RESET_RSRVD __BITS(31, 2) 297#define HW_CLKCTRL_RESET_CHIP __BIT(1) 298#define HW_CLKCTRL_RESET_DIG __BIT(0) 299 300/* 301 * CLKCTRL Status. 302 */ 303#define HW_CLKCTRL_STATUS 0x130 304 305#define HW_CLKCTRL_STATUS_CPU_LIMIT __BITS(31, 30) 306#define HW_CLKCTRL_STATUS_RSRVD __BITS(29, 0) 307 308/* 309 * CLKCTRL Version Register. 310 */ 311#define HW_CLKCTRL_VERSION 0x140 312 313#define HW_CLKCTRL_VERSION_MAJOR __BITS(31, 24) 314#define HW_CLKCTRL_VERSION_MINOR __BITS(23, 16) 315#define HW_CLKCTRL_VERSION_STEP __BITS(15, 0) 316 317#endif /* !_ARM_IMX_IMX23_CLKCTRLREG_H_ */ 318