1/* $NetBSD: gemini_gmacvar.h,v 1.2 2008/12/15 04:44:27 matt Exp $ */ 2/*- 3 * Copyright (c) 2008 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas <matt@3am-software.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#ifndef _ARM_GEMINI_GEMINI_GMACVAR_H 32#define _ARM_GEMINI_GEMINI_GMACVAR_H 33 34#include <sys/device.h> 35#include <sys/queue.h> 36#include <net/if.h> 37#include <net/if_media.h> 38#include <dev/mii/mii.h> 39#include <dev/mii/miivar.h> 40 41#include <arm/gemini/gemini_gmacreg.h> 42 43typedef struct gmac_hwqueue gmac_hwqueue_t; 44typedef struct gmac_hwqmem gmac_hwqmem_t; 45typedef struct gmac_mapcache gmac_mapcache_t; 46 47#define MAX_TXMAPS 256 48#define MIN_TXMAPS 16 49#define MAX_RXMAPS 128 50#define MIN_RXMAPS 8 51 52#define RXQ_NDESCS 256 53#define TXQ_NDESCS 128 54 55struct gmac_mapcache { 56 bus_dma_tag_t mc_dmat; 57 bus_size_t mc_mapsize; 58 size_t mc_nsegs; 59 size_t mc_free; 60 size_t mc_used; 61 size_t mc_max; 62 bus_dmamap_t mc_maps[0]; 63}; 64 65struct gmac_softc { 66 device_t sc_dev; 67 bus_space_tag_t sc_iot; 68 bus_space_handle_t sc_ioh; 69 bus_dma_tag_t sc_dmat; 70 71 /* 72 * MDIO state 73 */ 74 kmutex_t sc_mdiolock; 75 uint32_t sc_mdiobits; 76 device_t sc_gpio_dev; 77 uint8_t sc_gpio_mdclk; 78 uint8_t sc_gpio_mdin; 79 uint8_t sc_gpio_mdout; 80 81 /* 82 * What GMAC ports have attached? 83 */ 84 uint8_t sc_ports; 85 uint8_t sc_running; 86 87 /* 88 * The hardware free queue and software free queue are shared 89 * resources. As are the dmamap caches. 90 */ 91 gmac_hwqueue_t *sc_swfreeq; 92 gmac_hwqueue_t *sc_hwfreeq; 93 gmac_mapcache_t *sc_rxmaps; 94 gmac_mapcache_t *sc_txmaps; 95 size_t sc_swfree_min; /* min mbufs to keep on swfreeq */ 96 size_t sc_rxpkts_per_sec; 97 98 /* 99 * What interrupts are enabled for both ports? 100 */ 101 uint32_t sc_int_enabled[5]; 102 uint32_t sc_int_select[5]; 103}; 104 105struct gmac_attach_args { 106 bus_space_tag_t gma_iot; 107 bus_space_handle_t gma_ioh; 108 bus_dma_tag_t gma_dmat; 109 110 int gma_port; 111 int gma_phy; 112 int gma_intr; 113 114 mii_readreg_t gma_mii_readreg; 115 mii_writereg_t gma_mii_writereg; 116}; 117 118struct gmac_hwqmem { 119 bus_dma_tag_t hqm_dmat; 120 bus_dmamap_t hqm_dmamap; 121 gmac_mapcache_t *hqm_mc; 122 gmac_desc_t *hqm_base; 123 bus_size_t hqm_memsize; 124 bus_dma_segment_t hqm_segs[1]; 125 size_t hqm_ndesc; 126 size_t hqm_nqueue; 127 int hqm_nsegs; 128 uint8_t hqm_refs; 129 uint8_t hqm_flags; 130#define HQM_TX 0x0001 131#define HQM_RX 0x0000 132#define HQM_PRODUCER 0x0002 133#define HQM_CONSUMER 0x0000 134}; 135 136struct gmac_hwqueue { 137 gmac_desc_t *hwq_base; 138 gmac_hwqmem_t *hwq_hqm; 139 union { 140 SLIST_ENTRY(gmac_hwqueue) qun_link; 141 SLIST_HEAD(,gmac_hwqueue) qun_producers; 142 struct gmac_hwqueue *qun_producer; 143 } hwq_qun; 144#define hwq_link hwq_qun.qun_link 145#define hwq_producers hwq_qun.qun_producers 146#define hwq_producer hwq_qun.qun_producer 147 struct ifnet *hwq_ifp; 148 struct ifqueue hwq_ifq; 149 struct mbuf *hwq_rxmbuf; 150 struct mbuf **hwq_mp; 151 bus_space_tag_t hwq_iot; 152 bus_space_handle_t hwq_qrwptr_ioh; 153 /* 154 * These are in units of gmac_desc_t, not bytes. 155 */ 156 size_t hwq_qoff; /* offset in descriptors to start */ 157 uint16_t hwq_wptr; /* next descriptor to write */ 158 uint16_t hwq_rptr; /* next descriptor to read */ 159 uint16_t hwq_free; /* descriptors can be produced */ 160 uint16_t hwq_size; /* total number of descriptors */ 161 uint8_t hwq_ref; 162}; 163 164#ifdef _KERNEL 165gmac_hwqmem_t * 166 gmac_hwqmem_create(gmac_mapcache_t *, size_t, size_t, int); 167void gmac_hwqmem_destroy(gmac_hwqmem_t *); 168 169void gmac_hwqueue_destroy(gmac_hwqueue_t *); 170gmac_hwqueue_t * 171 gmac_hwqueue_create(gmac_hwqmem_t *, bus_space_tag_t, 172 bus_space_handle_t, bus_size_t, bus_size_t, size_t); 173 174gmac_desc_t * 175 gmac_hwqueue_desc(gmac_hwqueue_t *, size_t); 176void gmac_hwqueue_sync(gmac_hwqueue_t *); 177size_t gmac_hwqueue_consume(gmac_hwqueue_t *, size_t); 178void gmac_hwqueue_produce(gmac_hwqueue_t *, size_t); 179 180gmac_mapcache_t * 181 gmac_mapcache_create(bus_dma_tag_t, size_t, bus_size_t, int); 182void gmac_mapcache_destroy(gmac_mapcache_t **); 183int gmac_mapcache_fill(gmac_mapcache_t *, size_t); 184bus_dmamap_t 185 gmac_mapcache_get(gmac_mapcache_t *); 186void gmac_mapcache_put(gmac_mapcache_t *, bus_dmamap_t); 187 188size_t gmac_rxproduce(gmac_hwqueue_t *, size_t); 189void gmac_swfree_min_update(struct gmac_softc *); 190void gmac_intr_update(struct gmac_softc *); 191#endif 192 193#endif /* _ARM_GEMINI_GEMINI_GMACVAR_H */ 194