bcm53xx_board.c revision 1.4
1/* $NetBSD: bcm53xx_board.c,v 1.4 2012/10/03 19:18:40 matt Exp $ */ 2/*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include "opt_broadcom.h" 32 33#define _ARM32_BUS_DMA_PRIVATE 34 35#include <sys/cdefs.h> 36 37__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.4 2012/10/03 19:18:40 matt Exp $"); 38 39#include <sys/param.h> 40#include <sys/bus.h> 41#include <sys/cpu.h> 42#include <sys/device.h> 43 44#include <prop/proplib.h> 45 46#include <net/if.h> 47#include <net/if_ether.h> 48 49#define CRU_PRIVATE 50#define DDR_PRIVATE 51#define DMU_PRIVATE 52#define ARMCORE_PRIVATE 53#define SRAB_PRIVATE 54 55#include <arm/cortex/a9tmr_var.h> 56#include <arm/cortex/pl310_var.h> 57#include <arm/mainbus/mainbus.h> 58 59#include <arm/broadcom/bcm53xx_reg.h> 60#include <arm/broadcom/bcm53xx_var.h> 61 62bus_space_tag_t bcm53xx_ioreg_bst = &bcmgen_bs_tag; 63bus_space_handle_t bcm53xx_ioreg_bsh; 64bus_space_tag_t bcm53xx_armcore_bst = &bcmgen_bs_tag; 65bus_space_handle_t bcm53xx_armcore_bsh; 66 67static struct cpu_softc cpu_softc; 68static struct bcm53xx_clock_info clk_info; 69 70struct arm32_bus_dma_tag bcm53xx_dma_tag = { 71 _BUS_DMAMAP_FUNCS, 72 _BUS_DMAMEM_FUNCS, 73 _BUS_DMATAG_FUNCS, 74}; 75 76#ifdef BCM53XX_CONSOLE_EARLY 77#include <dev/ic/ns16550reg.h> 78#include <dev/ic/comreg.h> 79#include <dev/cons.h> 80 81static vaddr_t com_base; 82 83static inline uint32_t 84uart_read(bus_size_t o) 85{ 86 return *(volatile uint8_t *)(com_base + o); 87} 88 89static inline void 90uart_write(bus_size_t o, uint32_t v) 91{ 92 *(volatile uint8_t *)(com_base + o) = v; 93} 94 95static int 96bcm53xx_cngetc(dev_t dv) 97{ 98 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 99 return -1; 100 101 return uart_read(com_data) & 0xff; 102} 103 104static void 105bcm53xx_cnputc(dev_t dv, int c) 106{ 107 int timo = 150000; 108 109 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 110 ; 111 112 uart_write(com_data, c); 113 114 timo = 150000; 115 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 116 ; 117} 118 119static struct consdev bcm53xx_earlycons = { 120 .cn_putc = bcm53xx_cnputc, 121 .cn_getc = bcm53xx_cngetc, 122 .cn_pollc = nullcnpollc, 123}; 124#endif /* BCM53XX_CONSOLE_EARLY */ 125 126psize_t 127bcm53xx_memprobe(void) 128{ 129 bus_space_tag_t bst = bcm53xx_ioreg_bst; 130 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 131 132 /* 133 * First, let's read the magic DDR registers! 134 */ 135 const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01); 136 const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82); 137 const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86); 138 const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87); 139 140 /* 141 * Calculate chip parameters 142 * */ 143 const u_int rows = __SHIFTOUT(v01, CTL_01_MAX_ROW) 144 - __SHIFTOUT(v82, CTL_82_ROW_DIFF); 145 const u_int cols = __SHIFTOUT(v01, CTL_01_MAX_COL) 146 - __SHIFTOUT(v82, CTL_82_COL_DIFF); 147 const u_int banks_log2 = 3 - __SHIFTOUT(v82, CTL_82_BANK_DIFF); 148 149 /* 150 * For each chip select, increase the chip count if if is enabled. 151 */ 152 const u_int max_chips = __SHIFTOUT(v01, CTL_01_MAX_CHIP_SEL); 153 u_int cs_map = __SHIFTOUT(v86, CTL_86_CS_MAP); 154 u_int chips = 0; 155 156 for (u_int i = 0; cs_map != 0 && i < max_chips; i++, cs_map >>= 1) { 157 chips += (cs_map & 1); 158 } 159 160 /* get log2(ddr width) */ 161 162 const u_int ddr_width_log2 = (v87 & CTL_87_REDUC) ? 1 : 2; 163 164 /* 165 * Let's add up all the things that contribute to the size of a chip. 166 */ 167 const u_int chip_size_log2 = cols + rows + banks_log2 + ddr_width_log2; 168 169 /* 170 * Now our memory size is simply the number of chip shifted by the 171 * log2(chip_size). 172 */ 173 return (psize_t) chips << chip_size_log2; 174} 175 176static inline uint32_t 177bcm53xx_freq_calc(struct bcm53xx_clock_info *clk, 178 uint32_t pdiv, uint32_t ndiv_int, uint32_t ndiv_frac) 179{ 180 if (ndiv_frac == 0 && pdiv == 1) 181 return ndiv_int * clk->clk_ref; 182 183 uint64_t freq64 = ((uint64_t)ndiv_int << 30) + ndiv_frac; 184 freq64 *= clk->clk_ref; 185 if (pdiv > 1) 186 freq64 /= pdiv; 187 return (uint32_t) (freq64 >> 30); 188} 189 190static uint32_t 191bcm53xx_value_wrap(uint32_t value, uint32_t mask) 192{ 193 /* 194 * n is n except when n is 0 then n = mask + 1. 195 */ 196 return ((__SHIFTOUT(value, mask) - 1) & __SHIFTOUT(mask, mask)) + 1; 197} 198 199static void 200bcm53xx_genpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control5, 201 uint32_t control6, uint32_t control7) 202{ 203 const uint32_t pdiv = bcm53xx_value_wrap(control6, 204 GENPLL_CONTROL6_PDIV); 205 const uint32_t ndiv_int = bcm53xx_value_wrap(control5, 206 GENPLL_CONTROL5_NDIV_INT); 207 const uint32_t ndiv_frac = __SHIFTOUT(control5, 208 GENPLL_CONTROL5_NDIV_FRAC); 209 210 clk->clk_genpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 211 212 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control6, 213 GENPLL_CONTROL6_CH0_MDIV); 214 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control6, 215 GENPLL_CONTROL6_CH1_MDIV); 216 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control6, 217 GENPLL_CONTROL6_CH2_MDIV); 218 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control7, 219 GENPLL_CONTROL7_CH3_MDIV); 220 221 clk->clk_mac = clk->clk_genpll / ch0_mdiv; // GENPLL CH0 222 clk->clk_robo = clk->clk_genpll / ch1_mdiv; // GENPLL CH1 223 clk->clk_usb2 = clk->clk_genpll / ch2_mdiv; // GENPLL CH2 224 clk->clk_iproc = clk->clk_genpll / ch3_mdiv; // GENPLL CH3 225} 226 227static void 228bcm53xx_lcpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control1, 229 uint32_t control2) 230{ 231 const uint32_t pdiv = bcm53xx_value_wrap(control1, 232 LCPLL_CONTROL1_PDIV); 233 const uint32_t ndiv_int = bcm53xx_value_wrap(control1, 234 LCPLL_CONTROL1_NDIV_INT); 235 const uint32_t ndiv_frac = __SHIFTOUT(control1, 236 LCPLL_CONTROL1_NDIV_FRAC); 237 238 clk->clk_lcpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 239 240 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control2, 241 LCPLL_CONTROL2_CH0_MDIV); 242 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control2, 243 LCPLL_CONTROL2_CH1_MDIV); 244 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control2, 245 LCPLL_CONTROL2_CH2_MDIV); 246 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control2, 247 LCPLL_CONTROL2_CH3_MDIV); 248 249 clk->clk_pcie_ref = clk->clk_lcpll / ch0_mdiv; // LCPLL CH0 250 clk->clk_sdio = clk->clk_lcpll / ch1_mdiv; // LCPLL CH1 251 clk->clk_ddr_ref = clk->clk_lcpll / ch2_mdiv; // LCPLL CH2 252 clk->clk_axi = clk->clk_lcpll / ch3_mdiv; // LCPLL CH3 253} 254 255static void 256bcm53xx_usb_clock_init(struct bcm53xx_clock_info *clk, uint32_t usb2_control) 257{ 258 const uint32_t pdiv = bcm53xx_value_wrap(usb2_control, 259 USB2_CONTROL_PDIV); 260 const uint32_t ndiv = bcm53xx_value_wrap(usb2_control, 261 USB2_CONTROL_NDIV_INT); 262 263 uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv; 264 if (usb_ref != USB2_REF_CLK) { 265 /* 266 * USB Reference Clock isn't 1.92GHz. So we need to modify 267 * USB2_CONTROL to produce it. 268 */ 269 uint32_t new_ndiv = (USB2_REF_CLK / clk->clk_usb2) * pdiv; 270 usb2_control &= ~USB2_CONTROL_NDIV_INT; 271 usb2_control |= __SHIFTIN(new_ndiv, USB2_CONTROL_NDIV_INT); 272 273 // Allow Clocks to be modified 274 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 275 CRU_BASE + CRU_CLKSET_KEY, CRU_CLKSET_KEY_MAGIC); 276 277 // Update USB2 clock generator 278 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 279 CRU_BASE + CRU_USB2_CONTROL, usb2_control); 280 281 // Prevent Clock modification 282 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 283 CRU_BASE + CRU_CLKSET_KEY, 0); 284 285 usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv; 286 } 287 288 clk->clk_usb_ref = usb_ref; 289} 290 291 292static void 293bcm53xx_clock_init(struct bcm53xx_clock_info *clk) 294{ 295 clk->clk_ref = BCM53XX_REF_CLK; 296 clk->clk_sys = 8*clk->clk_ref; 297} 298 299/* 300 * F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2) 301 */ 302static void 303bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status, 304 uint32_t pll_dividers) 305{ 306 const bool clocking_4x = (pll_status & PLL_STATUS_CLOCKING_4X) != 0; 307 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV); 308 u_int pdiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_PDIV); 309 u_int ndiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_NDIV); 310 311 pdiv = ((pdiv - (clocking_4x ? 1 : 5)) & 7) + 1; 312 313 clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ); 314 clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div); 315} 316 317/* 318 * CPU_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref) 319 */ 320static void 321bcm53xx_get_cpu_freq(struct bcm53xx_clock_info *clk, 322 uint32_t pllarma, uint32_t pllarmb, uint32_t policy) 323{ 324 policy = __SHIFTOUT(policy, CLK_POLICY_FREQ_POLICY2); 325 326 if (policy == CLK_POLICY_REF_CLK) { 327 clk->clk_cpu = clk->clk_ref; 328 clk->clk_apb = clk->clk_cpu; 329 return; 330 } 331 332 if (policy == CLK_POLICY_SYS_CLK) { 333 clk->clk_cpu = clk->clk_sys; 334 clk->clk_apb = clk->clk_cpu / 4; 335 return; 336 } 337 338 const u_int pdiv = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_PDIV); 339 const u_int ndiv_int = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_NDIV_INT); 340 const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC); 341 // const u_int apb_clk_div = __SHIFTOUT(apb_clk_div, CLK_APB_DIV_VALUE)+1; 342 343 const u_int cpu_div = (policy == CLK_POLICY_ARM_PLL_CH0) ? 4 : 2; 344 345 clk->clk_cpu = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac) / cpu_div; 346 clk->clk_apb = clk->clk_cpu / 4; 347} 348 349struct bcm53xx_chip_state { 350 uint32_t bcs_lcpll_control1; 351 uint32_t bcs_lcpll_control2; 352 353 uint32_t bcs_genpll_control5; 354 uint32_t bcs_genpll_control6; 355 uint32_t bcs_genpll_control7; 356 357 uint32_t bcs_usb2_control; 358 359 uint32_t bcs_ddr_phy_ctl_pll_status; 360 uint32_t bcs_ddr_phy_ctl_pll_dividers; 361 362 uint32_t bcs_armcore_clk_policy; 363 uint32_t bcs_armcore_clk_pllarma; 364 uint32_t bcs_armcore_clk_pllarmb; 365}; 366 367static void 368bcm53xx_get_chip_ioreg_state(struct bcm53xx_chip_state *bcs, 369 bus_space_tag_t bst, bus_space_handle_t bsh) 370{ 371 bcs->bcs_lcpll_control1 = bus_space_read_4(bst, bsh, 372 DMU_BASE + DMU_LCPLL_CONTROL1); 373 bcs->bcs_lcpll_control2 = bus_space_read_4(bst, bsh, 374 DMU_BASE + DMU_LCPLL_CONTROL2); 375 376 bcs->bcs_genpll_control5 = bus_space_read_4(bst, bsh, 377 CRU_BASE + CRU_GENPLL_CONTROL5); 378 bcs->bcs_genpll_control6 = bus_space_read_4(bst, bsh, 379 CRU_BASE + CRU_GENPLL_CONTROL6); 380 bcs->bcs_genpll_control7 = bus_space_read_4(bst, bsh, 381 CRU_BASE + CRU_GENPLL_CONTROL7); 382 383 bcs->bcs_usb2_control = bus_space_read_4(bst, bsh, 384 CRU_BASE + CRU_USB2_CONTROL); 385 386 bcs->bcs_ddr_phy_ctl_pll_status = bus_space_read_4(bst, bsh, 387 DDR_BASE + DDR_PHY_CTL_PLL_STATUS); 388 bcs->bcs_ddr_phy_ctl_pll_dividers = bus_space_read_4(bst, bsh, 389 DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS); 390} 391 392static void 393bcm53xx_get_chip_armcore_state(struct bcm53xx_chip_state *bcs, 394 bus_space_tag_t bst, bus_space_handle_t bsh) 395{ 396 bcs->bcs_armcore_clk_policy = bus_space_read_4(bst, bsh, 397 ARMCORE_CLK_POLICY_FREQ); 398 bcs->bcs_armcore_clk_pllarma = bus_space_read_4(bst, bsh, 399 ARMCORE_CLK_PLLARMA); 400 bcs->bcs_armcore_clk_pllarmb = bus_space_read_4(bst, bsh, 401 ARMCORE_CLK_PLLARMB); 402} 403 404void 405bcm53xx_cpu_softc_init(struct cpu_info *ci) 406{ 407 struct cpu_softc * const cpu = ci->ci_softc; 408 409 cpu->cpu_ioreg_bst = bcm53xx_ioreg_bst; 410 cpu->cpu_ioreg_bsh = bcm53xx_ioreg_bsh; 411 412 cpu->cpu_armcore_bst = bcm53xx_armcore_bst; 413 cpu->cpu_armcore_bsh = bcm53xx_armcore_bsh; 414} 415 416void 417bcm53xx_print_clocks(void) 418{ 419#if defined(VERBOSE_ARM_INIT) 420 printf("ref clk = %u (%#x)\n", clk_info.clk_ref, clk_info.clk_ref); 421 printf("sys clk = %u (%#x)\n", clk_info.clk_sys, clk_info.clk_sys); 422 printf("lcpll clk = %u (%#x)\n", clk_info.clk_lcpll, clk_info.clk_lcpll); 423 printf("pcie ref clk = %u (%#x) [CH0]\n", clk_info.clk_pcie_ref, clk_info.clk_pcie_ref); 424 printf("sdio clk = %u (%#x) [CH1]\n", clk_info.clk_sdio, clk_info.clk_sdio); 425 printf("ddr ref clk = %u (%#x) [CH2]\n", clk_info.clk_ddr_ref, clk_info.clk_ddr_ref); 426 printf("axi clk = %u (%#x) [CH3]\n", clk_info.clk_axi, clk_info.clk_axi); 427 printf("genpll clk = %u (%#x)\n", clk_info.clk_genpll, clk_info.clk_genpll); 428 printf("mac clk = %u (%#x) [CH0]\n", clk_info.clk_mac, clk_info.clk_mac); 429 printf("robo clk = %u (%#x) [CH1]\n", clk_info.clk_robo, clk_info.clk_robo); 430 printf("usb2 clk = %u (%#x) [CH2]\n", clk_info.clk_usb2, clk_info.clk_usb2); 431 printf("iproc clk = %u (%#x) [CH3]\n", clk_info.clk_iproc, clk_info.clk_iproc); 432 printf("ddr clk = %u (%#x)\n", clk_info.clk_ddr, clk_info.clk_ddr); 433 printf("ddr mhz = %u (%#x)\n", clk_info.clk_ddr_mhz, clk_info.clk_ddr_mhz); 434 printf("cpu clk = %u (%#x)\n", clk_info.clk_cpu, clk_info.clk_cpu); 435 printf("apb clk = %u (%#x)\n", clk_info.clk_apb, clk_info.clk_apb); 436 printf("usb ref clk = %u (%#x)\n", clk_info.clk_usb_ref, clk_info.clk_usb_ref); 437#endif 438} 439 440void 441bcm53xx_bootstrap(vaddr_t iobase) 442{ 443 struct bcm53xx_chip_state bcs; 444 int error; 445 446#ifdef BCM53XX_CONSOLE_EARLY 447 com_base = iobase + CCA_UART0_BASE; 448 cn_tab = &bcm53xx_earlycons; 449#endif 450 451 bcm53xx_ioreg_bsh = (bus_space_handle_t) iobase; 452 error = bus_space_map(bcm53xx_ioreg_bst, BCM53XX_IOREG_PBASE, 453 BCM53XX_IOREG_SIZE, 0, &bcm53xx_ioreg_bsh); 454 if (error) 455 panic("%s: failed to map BCM53xx %s registers: %d", 456 __func__, "io", error); 457 458 bcm53xx_armcore_bsh = (bus_space_handle_t) iobase + BCM53XX_IOREG_SIZE; 459 error = bus_space_map(bcm53xx_armcore_bst, BCM53XX_ARMCORE_PBASE, 460 BCM53XX_ARMCORE_SIZE, 0, &bcm53xx_armcore_bsh); 461 if (error) 462 panic("%s: failed to map BCM53xx %s registers: %d", 463 __func__, "armcore", error); 464 465 curcpu()->ci_softc = &cpu_softc; 466 467 bcm53xx_get_chip_ioreg_state(&bcs, bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh); 468 bcm53xx_get_chip_armcore_state(&bcs, bcm53xx_armcore_bst, bcm53xx_armcore_bsh); 469 470 struct bcm53xx_clock_info * const clk = &clk_info; 471 472 bcm53xx_clock_init(clk); 473 bcm53xx_lcpll_clock_init(clk, bcs.bcs_lcpll_control1, 474 bcs.bcs_lcpll_control2); 475 bcm53xx_genpll_clock_init(clk, bcs.bcs_genpll_control5, 476 bcs.bcs_genpll_control6, bcs.bcs_genpll_control7); 477 bcm53xx_usb_clock_init(clk, bcs.bcs_usb2_control); 478 bcm53xx_get_ddr_freq(clk, bcs.bcs_ddr_phy_ctl_pll_status, 479 bcs.bcs_ddr_phy_ctl_pll_dividers); 480 bcm53xx_get_cpu_freq(clk, bcs.bcs_armcore_clk_pllarma, 481 bcs.bcs_armcore_clk_pllarmb, bcs.bcs_armcore_clk_policy); 482 483 curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu; 484 485 arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, ARMCORE_L2C_BASE); 486} 487 488#ifdef MULTIPROCESSOR 489void 490bcm53xx_cpu_hatch(struct cpu_info *ci) 491{ 492 a9tmr_init_cpu_clock(ci); 493} 494#endif 495 496void 497bcm53xx_device_register(device_t self, void *aux) 498{ 499 prop_dictionary_t dict = device_properties(self); 500 501 if (device_is_a(self, "armperiph") 502 && device_is_a(device_parent(self), "mainbus")) { 503 /* 504 * XXX KLUDGE ALERT XXX 505 * The iot mainbus supplies is completely wrong since it scales 506 * addresses by 2. The simpliest remedy is to replace with our 507 * bus space used for the armcore regisers (which armperiph uses). 508 */ 509 struct mainbus_attach_args * const mb = aux; 510 mb->mb_iot = bcm53xx_armcore_bst; 511 return; 512 } 513 514 /* 515 * We need to tell the A9 Global/Watchdog Timer 516 * what frequency it runs at. 517 */ 518 if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) { 519 /* 520 * This clock always runs at (arm_clk div 2) and only goes 521 * to timers that are part of the A9 MP core subsystem. 522 */ 523 prop_dictionary_set_uint32(dict, "frequency", 524 clk_info.clk_cpu / 2); 525 return; 526 } 527 528 if (device_is_a(self, "bcmeth")) { 529 const struct bcmccb_attach_args * const ccbaa = aux; 530 const uint8_t enaddr[ETHER_ADDR_LEN] = { 531 0x00, 0x01, 0x02, 0x03, 0x04, 532 0x05 + 2 * ccbaa->ccbaa_loc.loc_port, 533 }; 534 prop_data_t pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN); 535 KASSERT(pd != NULL); 536 if (prop_dictionary_set(device_properties(self), "mac-address", pd) == false) { 537 printf("WARNING: Unable to set mac-address property for %s\n", device_xname(self)); 538 } 539 prop_object_release(pd); 540 } 541} 542 543static kmutex_t srab_lock __cacheline_aligned; 544 545void 546bcm53xx_srab_init(void) 547{ 548 mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM); 549 550 bcm53xx_srab_write_4(0x0079, 0x90); // reset switch 551 for (u_int port = 0; port < 8; port++) { 552 /* per port control: no stp */ 553 bcm53xx_srab_write_4(port, 0x00); 554 } 555 bcm53xx_srab_write_4(0x0008, 0x1c); // IMP port (enab UC/MC/BC) 556 bcm53xx_srab_write_4(0x000e, 0xbb); // IMP port force-link 1G 557 bcm53xx_srab_write_4(0x005d, 0x7b); // port5 force-link 1G 558 bcm53xx_srab_write_4(0x005f, 0x7b); // port7 force-link 1G 559 bcm53xx_srab_write_4(0x000b, 0x7); // management mode 560 bcm53xx_srab_write_4(0x0203, 0x0); // disable BRCM tag 561 bcm53xx_srab_write_4(0x0200, 0x80); // enable IMP=port8 562} 563 564static inline void 565bcm53xx_srab_busywait(bus_space_tag_t bst, bus_space_handle_t bsh) 566{ 567 while (bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT) & SRA_GORDYN) { 568 delay(10); 569 } 570} 571 572uint32_t 573bcm53xx_srab_read_4(u_int pageoffset) 574{ 575 bus_space_tag_t bst = bcm53xx_ioreg_bst; 576 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 577 uint32_t rv; 578 579 mutex_spin_enter(&srab_lock); 580 581 bcm53xx_srab_busywait(bst, bsh); 582 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 583 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 584 bcm53xx_srab_busywait(bst, bsh); 585 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 586 587 mutex_spin_exit(&srab_lock); 588 return rv; 589} 590 591uint64_t 592bcm53xx_srab_read_8(u_int pageoffset) 593{ 594 bus_space_tag_t bst = bcm53xx_ioreg_bst; 595 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 596 uint64_t rv; 597 598 mutex_spin_enter(&srab_lock); 599 600 bcm53xx_srab_busywait(bst, bsh); 601 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 602 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 603 bcm53xx_srab_busywait(bst, bsh); 604 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDH); 605 rv <<= 32; 606 rv |= bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 607 608 mutex_spin_exit(&srab_lock); 609 return rv; 610} 611 612void 613bcm53xx_srab_write_4(u_int pageoffset, uint32_t val) 614{ 615 bus_space_tag_t bst = bcm53xx_ioreg_bst; 616 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 617 618 mutex_spin_enter(&srab_lock); 619 620 bcm53xx_srab_busywait(bst, bsh); 621 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 622 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 623 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 624 bcm53xx_srab_busywait(bst, bsh); 625 626 mutex_spin_exit(&srab_lock); 627} 628 629void 630bcm53xx_srab_write_8(u_int pageoffset, uint64_t val) 631{ 632 bus_space_tag_t bst = bcm53xx_ioreg_bst; 633 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 634 635 mutex_spin_enter(&srab_lock); 636 637 bcm53xx_srab_busywait(bst, bsh); 638 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 639 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDH, val >> 32); 640 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 641 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 642 bcm53xx_srab_busywait(bst, bsh); 643 mutex_spin_exit(&srab_lock); 644} 645