bcm53xx_board.c revision 1.11
1/* $NetBSD: bcm53xx_board.c,v 1.11 2013/02/08 23:24:02 matt Exp $ */ 2/*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include "opt_broadcom.h" 32 33#define _ARM32_BUS_DMA_PRIVATE 34 35#include <sys/cdefs.h> 36 37__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.11 2013/02/08 23:24:02 matt Exp $"); 38 39#include <sys/param.h> 40#include <sys/bus.h> 41#include <sys/cpu.h> 42#include <sys/device.h> 43 44#include <prop/proplib.h> 45 46#include <net/if.h> 47#include <net/if_ether.h> 48 49#define CRU_PRIVATE 50#define DDR_PRIVATE 51#define DMU_PRIVATE 52#define ARMCORE_PRIVATE 53#define SRAB_PRIVATE 54 55#include <arm/cortex/a9tmr_var.h> 56#include <arm/cortex/pl310_var.h> 57#include <arm/mainbus/mainbus.h> 58 59#include <arm/broadcom/bcm53xx_reg.h> 60#include <arm/broadcom/bcm53xx_var.h> 61 62bus_space_tag_t bcm53xx_ioreg_bst = &bcmgen_bs_tag; 63bus_space_handle_t bcm53xx_ioreg_bsh; 64bus_space_tag_t bcm53xx_armcore_bst = &bcmgen_bs_tag; 65bus_space_handle_t bcm53xx_armcore_bsh; 66 67static struct cpu_softc cpu_softc; 68 69struct arm32_dma_range bcm53xx_dma_ranges[2] = { 70 [0] = { 71 .dr_sysbase = 0x80000000, 72 .dr_busbase = 0x80000000, 73 .dr_len = 0x10000000, 74 }, [1] = { 75 .dr_sysbase = 0x90000000, 76 .dr_busbase = 0x90000000, 77 }, 78}; 79 80struct arm32_bus_dma_tag bcm53xx_dma_tag = { 81 ._ranges = bcm53xx_dma_ranges, 82 ._nranges = __arraycount(bcm53xx_dma_ranges), 83 _BUS_DMAMAP_FUNCS, 84 _BUS_DMAMEM_FUNCS, 85 _BUS_DMATAG_FUNCS, 86}; 87 88struct arm32_dma_range bcm53xx_coherent_dma_ranges[2] = { 89 [0] = { 90 .dr_sysbase = 0x80000000, 91 .dr_busbase = 0x80000000, 92 .dr_len = 0x10000000, 93 .dr_flags = _BUS_DMAMAP_COHERENT, 94#ifndef _ARM32_NEED_BUS_DMA_BOUNCE 95 }, [1] = { 96 .dr_sysbase = 0x90000000, 97 .dr_busbase = 0x90000000, 98#endif 99 }, 100}; 101 102struct arm32_bus_dma_tag bcm53xx_coherent_dma_tag = { 103 ._ranges = bcm53xx_coherent_dma_ranges, 104 ._nranges = __arraycount(bcm53xx_coherent_dma_ranges), 105 _BUS_DMAMAP_FUNCS, 106 _BUS_DMAMEM_FUNCS, 107 _BUS_DMATAG_FUNCS, 108}; 109 110#ifdef BCM53XX_CONSOLE_EARLY 111#include <dev/ic/ns16550reg.h> 112#include <dev/ic/comreg.h> 113#include <dev/cons.h> 114 115static vaddr_t com_base; 116 117static inline uint32_t 118uart_read(bus_size_t o) 119{ 120 return *(volatile uint8_t *)(com_base + o); 121} 122 123static inline void 124uart_write(bus_size_t o, uint32_t v) 125{ 126 *(volatile uint8_t *)(com_base + o) = v; 127} 128 129static int 130bcm53xx_cngetc(dev_t dv) 131{ 132 if ((uart_read(com_lsr) & LSR_RXRDY) == 0) 133 return -1; 134 135 return uart_read(com_data) & 0xff; 136} 137 138static void 139bcm53xx_cnputc(dev_t dv, int c) 140{ 141 int timo = 150000; 142 143 while ((uart_read(com_lsr) & LSR_TXRDY) == 0 && --timo > 0) 144 ; 145 146 uart_write(com_data, c); 147 148 timo = 150000; 149 while ((uart_read(com_lsr) & LSR_TSRE) == 0 && --timo > 0) 150 ; 151} 152 153static struct consdev bcm53xx_earlycons = { 154 .cn_putc = bcm53xx_cnputc, 155 .cn_getc = bcm53xx_cngetc, 156 .cn_pollc = nullcnpollc, 157}; 158#endif /* BCM53XX_CONSOLE_EARLY */ 159 160psize_t 161bcm53xx_memprobe(void) 162{ 163 bus_space_tag_t bst = bcm53xx_ioreg_bst; 164 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 165 166 /* 167 * First, let's read the magic DDR registers! 168 */ 169 const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01); 170 const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82); 171 const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86); 172 const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87); 173 174 /* 175 * Calculate chip parameters 176 * */ 177 const u_int rows = __SHIFTOUT(v01, CTL_01_MAX_ROW) 178 - __SHIFTOUT(v82, CTL_82_ROW_DIFF); 179 const u_int cols = __SHIFTOUT(v01, CTL_01_MAX_COL) 180 - __SHIFTOUT(v82, CTL_82_COL_DIFF); 181 const u_int banks_log2 = 3 - __SHIFTOUT(v82, CTL_82_BANK_DIFF); 182 183 /* 184 * For each chip select, increase the chip count if if is enabled. 185 */ 186 const u_int max_chips = __SHIFTOUT(v01, CTL_01_MAX_CHIP_SEL); 187 u_int cs_map = __SHIFTOUT(v86, CTL_86_CS_MAP); 188 u_int chips = 0; 189 190 for (u_int i = 0; cs_map != 0 && i < max_chips; i++, cs_map >>= 1) { 191 chips += (cs_map & 1); 192 } 193 194 /* get log2(ddr width) */ 195 196 const u_int ddr_width_log2 = (v87 & CTL_87_REDUC) ? 1 : 2; 197 198 /* 199 * Let's add up all the things that contribute to the size of a chip. 200 */ 201 const u_int chip_size_log2 = cols + rows + banks_log2 + ddr_width_log2; 202 203 /* 204 * Now our memory size is simply the number of chip shifted by the 205 * log2(chip_size). 206 */ 207 return (psize_t) chips << chip_size_log2; 208} 209 210static inline uint32_t 211bcm53xx_freq_calc(struct bcm53xx_clock_info *clk, 212 uint32_t pdiv, uint32_t ndiv_int, uint32_t ndiv_frac) 213{ 214 if (ndiv_frac == 0 && pdiv == 1) 215 return ndiv_int * clk->clk_ref; 216 217 uint64_t freq64 = ((uint64_t)ndiv_int << 30) + ndiv_frac; 218 freq64 *= clk->clk_ref; 219 if (pdiv > 1) 220 freq64 /= pdiv; 221 return (uint32_t) (freq64 >> 30); 222} 223 224static uint32_t 225bcm53xx_value_wrap(uint32_t value, uint32_t mask) 226{ 227 /* 228 * n is n except when n is 0 then n = mask + 1. 229 */ 230 return ((__SHIFTOUT(value, mask) - 1) & __SHIFTOUT(mask, mask)) + 1; 231} 232 233static void 234bcm53xx_genpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control5, 235 uint32_t control6, uint32_t control7) 236{ 237 const uint32_t pdiv = bcm53xx_value_wrap(control6, 238 GENPLL_CONTROL6_PDIV); 239 const uint32_t ndiv_int = bcm53xx_value_wrap(control5, 240 GENPLL_CONTROL5_NDIV_INT); 241 const uint32_t ndiv_frac = __SHIFTOUT(control5, 242 GENPLL_CONTROL5_NDIV_FRAC); 243 244 clk->clk_genpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 245 246 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control6, 247 GENPLL_CONTROL6_CH0_MDIV); 248 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control6, 249 GENPLL_CONTROL6_CH1_MDIV); 250 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control6, 251 GENPLL_CONTROL6_CH2_MDIV); 252 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control7, 253 GENPLL_CONTROL7_CH3_MDIV); 254 255 clk->clk_mac = clk->clk_genpll / ch0_mdiv; // GENPLL CH0 256 clk->clk_robo = clk->clk_genpll / ch1_mdiv; // GENPLL CH1 257 clk->clk_usb2 = clk->clk_genpll / ch2_mdiv; // GENPLL CH2 258 clk->clk_iproc = clk->clk_genpll / ch3_mdiv; // GENPLL CH3 259} 260 261static void 262bcm53xx_lcpll_clock_init(struct bcm53xx_clock_info *clk, uint32_t control1, 263 uint32_t control2) 264{ 265 const uint32_t pdiv = bcm53xx_value_wrap(control1, 266 LCPLL_CONTROL1_PDIV); 267 const uint32_t ndiv_int = bcm53xx_value_wrap(control1, 268 LCPLL_CONTROL1_NDIV_INT); 269 const uint32_t ndiv_frac = __SHIFTOUT(control1, 270 LCPLL_CONTROL1_NDIV_FRAC); 271 272 clk->clk_lcpll = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac); 273 274 const uint32_t ch0_mdiv = bcm53xx_value_wrap(control2, 275 LCPLL_CONTROL2_CH0_MDIV); 276 const uint32_t ch1_mdiv = bcm53xx_value_wrap(control2, 277 LCPLL_CONTROL2_CH1_MDIV); 278 const uint32_t ch2_mdiv = bcm53xx_value_wrap(control2, 279 LCPLL_CONTROL2_CH2_MDIV); 280 const uint32_t ch3_mdiv = bcm53xx_value_wrap(control2, 281 LCPLL_CONTROL2_CH3_MDIV); 282 283 clk->clk_pcie_ref = clk->clk_lcpll / ch0_mdiv; // LCPLL CH0 284 clk->clk_sdio = clk->clk_lcpll / ch1_mdiv; // LCPLL CH1 285 clk->clk_ddr_ref = clk->clk_lcpll / ch2_mdiv; // LCPLL CH2 286 clk->clk_axi = clk->clk_lcpll / ch3_mdiv; // LCPLL CH3 287} 288 289static void 290bcm53xx_usb_clock_init(struct bcm53xx_clock_info *clk, uint32_t usb2_control) 291{ 292 const uint32_t pdiv = bcm53xx_value_wrap(usb2_control, 293 USB2_CONTROL_PDIV); 294 const uint32_t ndiv = bcm53xx_value_wrap(usb2_control, 295 USB2_CONTROL_NDIV_INT); 296 297 uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv; 298 if (usb_ref != USB2_REF_CLK) { 299 /* 300 * USB Reference Clock isn't 1.92GHz. So we need to modify 301 * USB2_CONTROL to produce it. 302 */ 303 uint32_t new_ndiv = (USB2_REF_CLK / clk->clk_usb2) * pdiv; 304 usb2_control &= ~USB2_CONTROL_NDIV_INT; 305 usb2_control |= __SHIFTIN(new_ndiv, USB2_CONTROL_NDIV_INT); 306 307 // Allow Clocks to be modified 308 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 309 CRU_BASE + CRU_CLKSET_KEY, CRU_CLKSET_KEY_MAGIC); 310 311 // Update USB2 clock generator 312 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 313 CRU_BASE + CRU_USB2_CONTROL, usb2_control); 314 315 // Prevent Clock modification 316 bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh, 317 CRU_BASE + CRU_CLKSET_KEY, 0); 318 319 usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv; 320 } 321 322 clk->clk_usb_ref = usb_ref; 323} 324 325 326static void 327bcm53xx_clock_init(struct bcm53xx_clock_info *clk) 328{ 329 clk->clk_ref = BCM53XX_REF_CLK; 330 clk->clk_sys = 8*clk->clk_ref; 331} 332 333/* 334 * F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2) 335 */ 336static void 337bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status, 338 uint32_t pll_dividers) 339{ 340 const bool clocking_4x = (pll_status & PLL_STATUS_CLOCKING_4X) != 0; 341 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV); 342 u_int pdiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_PDIV); 343 u_int ndiv = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_NDIV); 344 345 pdiv = ((pdiv - (clocking_4x ? 1 : 5)) & 7) + 1; 346 347 clk->clk_ddr_mhz = __SHIFTOUT(pll_status, PLL_STATUS_MHZ); 348 clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div); 349} 350 351/* 352 * CPU_CLK = (1 / pdiv) * (ndiv_int + (ndiv_frac / 0x40000000)) x F(ref) 353 */ 354static void 355bcm53xx_get_cpu_freq(struct bcm53xx_clock_info *clk, 356 uint32_t pllarma, uint32_t pllarmb, uint32_t policy) 357{ 358 policy = __SHIFTOUT(policy, CLK_POLICY_FREQ_POLICY2); 359 360 if (policy == CLK_POLICY_REF_CLK) { 361 clk->clk_cpu = clk->clk_ref; 362 clk->clk_apb = clk->clk_cpu; 363 return; 364 } 365 366 if (policy == CLK_POLICY_SYS_CLK) { 367 clk->clk_cpu = clk->clk_sys; 368 clk->clk_apb = clk->clk_cpu / 4; 369 return; 370 } 371 372 const u_int pdiv = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_PDIV); 373 const u_int ndiv_int = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_NDIV_INT); 374 const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC); 375 // const u_int apb_clk_div = __SHIFTOUT(apb_clk_div, CLK_APB_DIV_VALUE)+1; 376 377 const u_int cpu_div = (policy == CLK_POLICY_ARM_PLL_CH0) ? 4 : 2; 378 379 clk->clk_cpu = bcm53xx_freq_calc(clk, pdiv, ndiv_int, ndiv_frac) / cpu_div; 380 clk->clk_apb = clk->clk_cpu / 4; 381} 382 383struct bcm53xx_chip_state { 384 uint32_t bcs_lcpll_control1; 385 uint32_t bcs_lcpll_control2; 386 387 uint32_t bcs_genpll_control5; 388 uint32_t bcs_genpll_control6; 389 uint32_t bcs_genpll_control7; 390 391 uint32_t bcs_usb2_control; 392 393 uint32_t bcs_ddr_phy_ctl_pll_status; 394 uint32_t bcs_ddr_phy_ctl_pll_dividers; 395 396 uint32_t bcs_armcore_clk_policy; 397 uint32_t bcs_armcore_clk_pllarma; 398 uint32_t bcs_armcore_clk_pllarmb; 399}; 400 401static void 402bcm53xx_get_chip_ioreg_state(struct bcm53xx_chip_state *bcs, 403 bus_space_tag_t bst, bus_space_handle_t bsh) 404{ 405 bcs->bcs_lcpll_control1 = bus_space_read_4(bst, bsh, 406 DMU_BASE + DMU_LCPLL_CONTROL1); 407 bcs->bcs_lcpll_control2 = bus_space_read_4(bst, bsh, 408 DMU_BASE + DMU_LCPLL_CONTROL2); 409 410 bcs->bcs_genpll_control5 = bus_space_read_4(bst, bsh, 411 CRU_BASE + CRU_GENPLL_CONTROL5); 412 bcs->bcs_genpll_control6 = bus_space_read_4(bst, bsh, 413 CRU_BASE + CRU_GENPLL_CONTROL6); 414 bcs->bcs_genpll_control7 = bus_space_read_4(bst, bsh, 415 CRU_BASE + CRU_GENPLL_CONTROL7); 416 417 bcs->bcs_usb2_control = bus_space_read_4(bst, bsh, 418 CRU_BASE + CRU_USB2_CONTROL); 419 420 bcs->bcs_ddr_phy_ctl_pll_status = bus_space_read_4(bst, bsh, 421 DDR_BASE + DDR_PHY_CTL_PLL_STATUS); 422 bcs->bcs_ddr_phy_ctl_pll_dividers = bus_space_read_4(bst, bsh, 423 DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS); 424} 425 426static void 427bcm53xx_get_chip_armcore_state(struct bcm53xx_chip_state *bcs, 428 bus_space_tag_t bst, bus_space_handle_t bsh) 429{ 430 bcs->bcs_armcore_clk_policy = bus_space_read_4(bst, bsh, 431 ARMCORE_CLK_POLICY_FREQ); 432 bcs->bcs_armcore_clk_pllarma = bus_space_read_4(bst, bsh, 433 ARMCORE_CLK_PLLARMA); 434 bcs->bcs_armcore_clk_pllarmb = bus_space_read_4(bst, bsh, 435 ARMCORE_CLK_PLLARMB); 436} 437 438void 439bcm53xx_cpu_softc_init(struct cpu_info *ci) 440{ 441 struct cpu_softc * const cpu = ci->ci_softc; 442 443 cpu->cpu_ioreg_bst = bcm53xx_ioreg_bst; 444 cpu->cpu_ioreg_bsh = bcm53xx_ioreg_bsh; 445 446 cpu->cpu_armcore_bst = bcm53xx_armcore_bst; 447 cpu->cpu_armcore_bsh = bcm53xx_armcore_bsh; 448} 449 450void 451bcm53xx_print_clocks(void) 452{ 453#if defined(VERBOSE_ARM_INIT) 454 const struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 455 printf("ref clk = %u (%#x)\n", clk->clk_ref, clk->clk_ref); 456 printf("sys clk = %u (%#x)\n", clk->clk_sys, clk->clk_sys); 457 printf("lcpll clk = %u (%#x)\n", clk->clk_lcpll, clk->clk_lcpll); 458 printf("pcie ref clk = %u (%#x) [CH0]\n", clk->clk_pcie_ref, clk->clk_pcie_ref); 459 printf("sdio clk = %u (%#x) [CH1]\n", clk->clk_sdio, clk->clk_sdio); 460 printf("ddr ref clk = %u (%#x) [CH2]\n", clk->clk_ddr_ref, clk->clk_ddr_ref); 461 printf("axi clk = %u (%#x) [CH3]\n", clk->clk_axi, clk->clk_axi); 462 printf("genpll clk = %u (%#x)\n", clk->clk_genpll, clk->clk_genpll); 463 printf("mac clk = %u (%#x) [CH0]\n", clk->clk_mac, clk->clk_mac); 464 printf("robo clk = %u (%#x) [CH1]\n", clk->clk_robo, clk->clk_robo); 465 printf("usb2 clk = %u (%#x) [CH2]\n", clk->clk_usb2, clk->clk_usb2); 466 printf("iproc clk = %u (%#x) [CH3]\n", clk->clk_iproc, clk->clk_iproc); 467 printf("ddr clk = %u (%#x)\n", clk->clk_ddr, clk->clk_ddr); 468 printf("ddr mhz = %u (%#x)\n", clk->clk_ddr_mhz, clk->clk_ddr_mhz); 469 printf("cpu clk = %u (%#x)\n", clk->clk_cpu, clk->clk_cpu); 470 printf("apb clk = %u (%#x)\n", clk->clk_apb, clk->clk_apb); 471 printf("usb ref clk = %u (%#x)\n", clk->clk_usb_ref, clk->clk_usb_ref); 472#endif 473} 474 475void 476bcm53xx_bootstrap(vaddr_t iobase) 477{ 478 struct bcm53xx_chip_state bcs; 479 int error; 480 481#ifdef BCM53XX_CONSOLE_EARLY 482 com_base = iobase + CCA_UART0_BASE; 483 cn_tab = &bcm53xx_earlycons; 484#endif 485 486 bcm53xx_ioreg_bsh = (bus_space_handle_t) iobase; 487 error = bus_space_map(bcm53xx_ioreg_bst, BCM53XX_IOREG_PBASE, 488 BCM53XX_IOREG_SIZE, 0, &bcm53xx_ioreg_bsh); 489 if (error) 490 panic("%s: failed to map BCM53xx %s registers: %d", 491 __func__, "io", error); 492 493 bcm53xx_armcore_bsh = (bus_space_handle_t) iobase + BCM53XX_IOREG_SIZE; 494 error = bus_space_map(bcm53xx_armcore_bst, BCM53XX_ARMCORE_PBASE, 495 BCM53XX_ARMCORE_SIZE, 0, &bcm53xx_armcore_bsh); 496 if (error) 497 panic("%s: failed to map BCM53xx %s registers: %d", 498 __func__, "armcore", error); 499 500 curcpu()->ci_softc = &cpu_softc; 501 502 bcm53xx_get_chip_ioreg_state(&bcs, bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh); 503 bcm53xx_get_chip_armcore_state(&bcs, bcm53xx_armcore_bst, bcm53xx_armcore_bsh); 504 505 struct bcm53xx_clock_info * const clk = &cpu_softc.cpu_clk; 506 507 bcm53xx_clock_init(clk); 508 bcm53xx_lcpll_clock_init(clk, bcs.bcs_lcpll_control1, 509 bcs.bcs_lcpll_control2); 510 bcm53xx_genpll_clock_init(clk, bcs.bcs_genpll_control5, 511 bcs.bcs_genpll_control6, bcs.bcs_genpll_control7); 512 bcm53xx_usb_clock_init(clk, bcs.bcs_usb2_control); 513 bcm53xx_get_ddr_freq(clk, bcs.bcs_ddr_phy_ctl_pll_status, 514 bcs.bcs_ddr_phy_ctl_pll_dividers); 515 bcm53xx_get_cpu_freq(clk, bcs.bcs_armcore_clk_pllarma, 516 bcs.bcs_armcore_clk_pllarmb, bcs.bcs_armcore_clk_policy); 517 518 curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu; 519 520 arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, ARMCORE_L2C_BASE); 521} 522 523void 524bcm53xx_dma_bootstrap(psize_t memsize) 525{ 526 if (memsize < 256*1024*1024) { 527 bcm53xx_dma_ranges[0].dr_len = memsize; 528 bcm53xx_coherent_dma_ranges[0].dr_len = memsize; 529 bcm53xx_dma_tag._nranges = 1; 530#ifdef _ARM32_NEED_BUS_DMA_BOUNCE 531 bcm53xx_coherent_dma_tag._nranges = 1; 532#endif 533 } else { 534 /* 535 * By setting up two ranges, bus_dmamem_alloc will always 536 * try to allocate from range 0 first resulting in allocations 537 * below 256MB which for PCI and GMAC are coherent. 538 */ 539 bcm53xx_dma_ranges[1].dr_len = memsize - 0x10000000; 540#ifdef _ARM32_NEED_BUS_DMA_BOUNCE 541 bcm53xx_coherent_dma_ranges[1].dr_len = memsize - 0x10000000; 542#endif 543 } 544 KASSERT(bcm53xx_dma_tag._ranges[0].dr_flags == 0); 545 KASSERT(bcm53xx_coherent_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT); 546} 547 548#ifdef MULTIPROCESSOR 549void 550bcm53xx_cpu_hatch(struct cpu_info *ci) 551{ 552 a9tmr_init_cpu_clock(ci); 553} 554#endif 555 556void 557bcm53xx_device_register(device_t self, void *aux) 558{ 559 prop_dictionary_t dict = device_properties(self); 560 561 if (device_is_a(self, "armperiph") 562 && device_is_a(device_parent(self), "mainbus")) { 563 /* 564 * XXX KLUDGE ALERT XXX 565 * The iot mainbus supplies is completely wrong since it scales 566 * addresses by 2. The simpliest remedy is to replace with our 567 * bus space used for the armcore regisers (which armperiph uses). 568 */ 569 struct mainbus_attach_args * const mb = aux; 570 mb->mb_iot = bcm53xx_armcore_bst; 571 return; 572 } 573 574 /* 575 * We need to tell the A9 Global/Watchdog Timer 576 * what frequency it runs at. 577 */ 578 if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) { 579 /* 580 * This clock always runs at (arm_clk div 2) and only goes 581 * to timers that are part of the A9 MP core subsystem. 582 */ 583 prop_dictionary_set_uint32(dict, "frequency", 584 cpu_softc.cpu_clk.clk_cpu / 2); 585 return; 586 } 587 588 if (device_is_a(self, "bcmeth")) { 589 const struct bcmccb_attach_args * const ccbaa = aux; 590 const uint8_t enaddr[ETHER_ADDR_LEN] = { 591 0x00, 0x01, 0x02, 0x03, 0x04, 592 0x05 + 2 * ccbaa->ccbaa_loc.loc_port, 593 }; 594 prop_data_t pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN); 595 KASSERT(pd != NULL); 596 if (prop_dictionary_set(device_properties(self), "mac-address", pd) == false) { 597 printf("WARNING: Unable to set mac-address property for %s\n", device_xname(self)); 598 } 599 prop_object_release(pd); 600 } 601} 602 603static kmutex_t srab_lock __cacheline_aligned; 604 605void 606bcm53xx_srab_init(void) 607{ 608 mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM); 609 610 bcm53xx_srab_write_4(0x0079, 0x90); // reset switch 611 for (u_int port = 0; port < 8; port++) { 612 /* per port control: no stp */ 613 bcm53xx_srab_write_4(port, 0x00); 614 } 615 bcm53xx_srab_write_4(0x0008, 0x1c); // IMP port (enab UC/MC/BC) 616 bcm53xx_srab_write_4(0x000e, 0xbb); // IMP port force-link 1G 617 bcm53xx_srab_write_4(0x005d, 0x7b); // port5 force-link 1G 618 bcm53xx_srab_write_4(0x005f, 0x7b); // port7 force-link 1G 619 bcm53xx_srab_write_4(0x000b, 0x7); // management mode 620 bcm53xx_srab_write_4(0x0203, 0x0); // disable BRCM tag 621 bcm53xx_srab_write_4(0x0200, 0x80); // enable IMP=port8 622} 623 624static inline void 625bcm53xx_srab_busywait(bus_space_tag_t bst, bus_space_handle_t bsh) 626{ 627 while (bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT) & SRA_GORDYN) { 628 delay(10); 629 } 630} 631 632uint32_t 633bcm53xx_srab_read_4(u_int pageoffset) 634{ 635 bus_space_tag_t bst = bcm53xx_ioreg_bst; 636 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 637 uint32_t rv; 638 639 mutex_spin_enter(&srab_lock); 640 641 bcm53xx_srab_busywait(bst, bsh); 642 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 643 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 644 bcm53xx_srab_busywait(bst, bsh); 645 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 646 647 mutex_spin_exit(&srab_lock); 648 return rv; 649} 650 651uint64_t 652bcm53xx_srab_read_8(u_int pageoffset) 653{ 654 bus_space_tag_t bst = bcm53xx_ioreg_bst; 655 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 656 uint64_t rv; 657 658 mutex_spin_enter(&srab_lock); 659 660 bcm53xx_srab_busywait(bst, bsh); 661 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 662 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN); 663 bcm53xx_srab_busywait(bst, bsh); 664 rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDH); 665 rv <<= 32; 666 rv |= bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL); 667 668 mutex_spin_exit(&srab_lock); 669 return rv; 670} 671 672void 673bcm53xx_srab_write_4(u_int pageoffset, uint32_t val) 674{ 675 bus_space_tag_t bst = bcm53xx_ioreg_bst; 676 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 677 678 mutex_spin_enter(&srab_lock); 679 680 bcm53xx_srab_busywait(bst, bsh); 681 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 682 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 683 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 684 bcm53xx_srab_busywait(bst, bsh); 685 686 mutex_spin_exit(&srab_lock); 687} 688 689void 690bcm53xx_srab_write_8(u_int pageoffset, uint64_t val) 691{ 692 bus_space_tag_t bst = bcm53xx_ioreg_bst; 693 bus_space_handle_t bsh = bcm53xx_ioreg_bsh; 694 695 mutex_spin_enter(&srab_lock); 696 697 bcm53xx_srab_busywait(bst, bsh); 698 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val); 699 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDH, val >> 32); 700 bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT, 701 __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN); 702 bcm53xx_srab_busywait(bst, bsh); 703 mutex_spin_exit(&srab_lock); 704} 705