1/*	$NetBSD: bcm2835_pwm.c,v 1.4 2021/01/27 03:10:19 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2015 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Michael van Elst
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Driver for BCM2835 Pulse Width Modulator
34 *
35 * Each channel can be allocated and used individually, but
36 * for FIFO usage, both channels must to be requested.
37 */
38
39#include <sys/cdefs.h>
40__KERNEL_RCSID(0, "$NetBSD: bcm2835_pwm.c,v 1.4 2021/01/27 03:10:19 thorpej Exp $");
41
42#include "bcmdmac.h"
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/device.h>
47#include <sys/kernel.h>
48#include <sys/bus.h>
49#include <sys/atomic.h>
50#include <sys/intr.h>
51
52#include <arm/broadcom/bcm2835reg.h>
53
54#include <arm/broadcom/bcm2835_pwm.h>
55
56#include <dev/fdt/fdtvar.h>
57
58struct bcm_pwm_channel {
59	struct bcm2835pwm_softc *sc;
60	uint32_t ctlmask, stamask, gapomask;
61	int rng, dat;
62	bool inuse;
63	uint32_t ctlsave, rngsave, datsave;
64};
65
66struct bcm2835pwm_softc {
67	device_t		sc_dev;
68
69	bus_space_tag_t		sc_iot;
70	bus_space_handle_t	sc_ioh;
71	bus_addr_t		sc_iob;
72
73	struct clk		*sc_clk;
74	int			sc_clockrate;
75	struct bcm_pwm_channel	sc_channels[2];
76	kmutex_t		sc_lock;
77};
78
79#define PWM_WRITE(sc, reg, val) \
80	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
81#define PWM_READ(sc, reg) \
82	bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
83
84static int bcmpwm_match(device_t, cfdata_t, void *);
85static void bcmpwm_attach(device_t, device_t, void *);
86static int bcmpwm_wait(struct bcm2835pwm_softc *);
87
88CFATTACH_DECL_NEW(bcmpwm, sizeof(struct bcm2835pwm_softc),
89    bcmpwm_match, bcmpwm_attach, NULL, NULL);
90
91static const struct device_compatible_entry compat_data[] = {
92	{ .compat = "brcm,bcm2835-pwm" },
93	DEVICE_COMPAT_EOL
94};
95
96/* ARGSUSED */
97static int
98bcmpwm_match(device_t parent, cfdata_t match, void *aux)
99{
100	struct fdt_attach_args * const faa = aux;
101
102	return of_compatible_match(faa->faa_phandle, compat_data);
103}
104
105static void
106bcmpwm_attach(device_t parent, device_t self, void *aux)
107{
108	struct bcm2835pwm_softc *sc = device_private(self);
109	struct fdt_attach_args * const faa = aux;
110	const int phandle = faa->faa_phandle;
111	bus_size_t size;
112
113	sc->sc_dev = self;
114	sc->sc_iot = faa->faa_bst;
115
116	int error = fdtbus_get_reg(phandle, 0, &sc->sc_iob, &size);
117	if (error) {
118		aprint_error(": failed to get registers\n");
119		return;
120	}
121
122	if (bus_space_map(sc->sc_iot, sc->sc_iob, size, 0,
123	    &sc->sc_ioh)) {
124		aprint_error_dev(sc->sc_dev, "unable to map device\n");
125		return;
126	}
127
128	sc->sc_clk = fdtbus_clock_get_index(phandle, 0);
129	if (sc->sc_clk == NULL) {
130		aprint_error(": couldn't get clk\n");
131		return;
132	}
133
134	error = clk_enable(sc->sc_clk);
135	if (error != 0) {
136		aprint_error(": couldn't enable clk\n");
137		return;
138	}
139
140	aprint_naive("\n");
141	aprint_normal(": Pulse Width Modulator\n");
142
143	sc->sc_clockrate = clk_get_rate(sc->sc_clk);
144
145	sc->sc_channels[0].sc = sc;
146	sc->sc_channels[0].ctlmask = PWM_CTL_MSEN1 | PWM_CTL_USEF1 |
147				     PWM_CTL_POLA1 | PWM_CTL_SBIT1 |
148				     PWM_CTL_RPTL1 | PWM_CTL_MODE1 |
149				     PWM_CTL_PWEN1;
150	sc->sc_channels[0].stamask = PWM_STA_STA1;
151	sc->sc_channels[0].gapomask = PWM_STA_GAPO1;
152	sc->sc_channels[0].rng = PWM_RNG1;
153	sc->sc_channels[0].dat = PWM_DAT1;
154
155	sc->sc_channels[1].sc = sc;
156	sc->sc_channels[1].ctlmask = PWM_CTL_MSEN2 | PWM_CTL_USEF2 |
157				     PWM_CTL_POLA2 | PWM_CTL_SBIT2 |
158				     PWM_CTL_RPTL2 | PWM_CTL_MODE2 |
159				     PWM_CTL_PWEN2;
160	sc->sc_channels[1].stamask = PWM_STA_STA2;
161	sc->sc_channels[1].gapomask = PWM_STA_GAPO2;
162	sc->sc_channels[1].rng = PWM_RNG2;
163	sc->sc_channels[1].dat = PWM_DAT2;
164
165	/* The PWM hardware can be used by vcaudio if the
166	 * analog output is selected
167	 */
168	sc->sc_channels[0].inuse = false;
169	sc->sc_channels[1].inuse = false;
170
171	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
172
173	/* Success!  */
174
175	return;
176}
177
178struct bcm_pwm_channel *
179bcm_pwm_alloc(int num)
180{
181	struct bcm2835pwm_softc *sc;
182	device_t dev;
183	struct bcm_pwm_channel *pwm;
184
185	dev = device_find_by_driver_unit("bcmpwm", 0);
186	if (dev == NULL)
187		return NULL;
188	sc = device_private(dev);
189
190	if (num < 0 || num >= __arraycount(sc->sc_channels))
191		return NULL;
192
193	pwm = &sc->sc_channels[num];
194
195	mutex_enter(&sc->sc_lock);
196	if (pwm->inuse)
197		pwm = NULL;
198	else
199		pwm->inuse = true;
200	mutex_exit(&sc->sc_lock);
201
202	if (pwm) {
203		pwm->datsave = PWM_READ(pwm->sc, pwm->dat);
204		pwm->ctlsave = PWM_READ(pwm->sc, PWM_CTL);
205		pwm->rngsave = PWM_READ(pwm->sc, pwm->rng);
206	}
207
208	return pwm;
209}
210
211void
212bcm_pwm_free(struct bcm_pwm_channel *pwm)
213{
214	struct bcm2835pwm_softc *sc = pwm->sc;
215
216	KASSERT(pwm->inuse);
217
218	PWM_WRITE(pwm->sc, pwm->rng, pwm->rngsave);
219	PWM_WRITE(pwm->sc, PWM_CTL, pwm->ctlsave & ~PWM_CTL_WRITEZERO);
220	PWM_WRITE(pwm->sc, pwm->dat, pwm->datsave);
221
222	mutex_enter(&sc->sc_lock);
223	pwm->inuse = false;
224	mutex_exit(&sc->sc_lock);
225}
226
227void
228bcm_pwm_control(struct bcm_pwm_channel *pwm, uint32_t ctl, uint32_t rng)
229{
230	struct bcm2835pwm_softc *sc = pwm->sc;
231	uint32_t w;
232
233	KASSERT(pwm->inuse);
234
235	/* set control bits like for channel 0
236	 * there are generic bit definitions that the caller can use.
237	 */
238	w = PWM_READ(pwm->sc, PWM_CTL);
239	ctl = (w & ~pwm->ctlmask) | __SHIFTIN(ctl, pwm->ctlmask);
240
241	/* when FIFO usage gets enabled but wasn't clear the FIFO */
242	if ((w & (PWM_CTL_USEF1|PWM_CTL_USEF2)) == 0 &&
243	    (ctl & (PWM_CTL_USEF1|PWM_CTL_USEF2)) != 0)
244		ctl |= PWM_CTL_CLRF1;
245
246	PWM_WRITE(sc, pwm->rng, rng);
247	PWM_WRITE(sc, PWM_CTL, ctl & ~PWM_CTL_WRITEZERO);
248}
249
250uint32_t
251bcm_pwm_status(struct bcm_pwm_channel *pwm)
252{
253	uint32_t w;
254	uint32_t common = PWM_STA_BERR | PWM_STA_RERR1 |
255			  PWM_STA_WERR1 | PWM_STA_EMPT1 | PWM_STA_FULL1;
256
257	/* return status bits like for channel 0
258	 * there are generic bit definitions that the caller can use.
259	 *
260	 * The BERR bit is returned for both channels.
261	 */
262	w = PWM_READ(pwm->sc, PWM_STA);
263	PWM_WRITE(pwm->sc, PWM_STA, w &
264		(pwm->stamask | pwm->gapomask | common));
265
266	w = __SHIFTIN(__SHIFTOUT(w, pwm->stamask), PWM_STA_STA)
267	  | __SHIFTIN(__SHIFTOUT(w, pwm->gapomask), PWM_STA_GAPO)
268	  | (w & common);
269
270	return w;
271}
272
273static int
274bcmpwm_wait(struct bcm2835pwm_softc *sc)
275{
276	int i;
277	uint32_t s;
278
279	for (i=0; i<1000; ++i) {
280		s = PWM_READ(sc, PWM_STA);
281		if ((s & PWM_STA_FULL1) == 0)
282			break;
283		delay(1);
284	}
285	if (i >= 1000)
286		return -1;
287
288	return 0;
289}
290
291int
292bcm_pwm_write(struct bcm_pwm_channel *pwm, uint32_t *data1, uint32_t *data2,
293    int len)
294{
295	struct bcm2835pwm_softc *sc = pwm->sc;
296	int n;
297	uint32_t r;
298	bool even = false;
299
300	KASSERT(pwm->inuse);
301
302	n = len;
303	while (n > 0) {
304		if (bcmpwm_wait(sc))
305			break;
306		r = even ? *data2++ : *data1++;
307		PWM_WRITE(sc, PWM_FIFO, r);
308		if (data2 != NULL)
309			even = !even;
310		--n;
311	}
312
313	return len - n;
314}
315
316void
317bcm_pwm_set(struct bcm_pwm_channel *pwm, uint32_t w)
318{
319	struct bcm2835pwm_softc *sc = pwm->sc;
320
321	PWM_WRITE(sc, pwm->dat, w);
322}
323
324int
325bcm_pwm_flush(struct bcm_pwm_channel *pwm)
326{
327	struct bcm2835pwm_softc *sc = pwm->sc;
328
329	return bcmpwm_wait(sc) ? EIO : 0;
330}
331
332void
333bcm_pwm_dma_enable(struct bcm_pwm_channel *pwm, bool enable)
334{
335	struct bcm2835pwm_softc *sc = pwm->sc;
336	uint32_t w;
337
338#if 0
339	w = PWM_READ(sc, PWM_DMAC);
340	if (enable)
341		w |= PWM_DMAC_ENAB;
342	else
343		w &= ~PWM_DMAC_ENAB;
344#else
345	w = (enable ? PWM_DMAC_ENAB : 0)
346	  | __SHIFTIN(7, PWM_DMAC_PANIC)
347	  | __SHIFTIN(7, PWM_DMAC_DREQ);
348#endif
349	PWM_WRITE(sc, PWM_DMAC, w & ~PWM_DMAC_WRITEZERO);
350}
351
352uint32_t
353bcm_pwm_dma_address(struct bcm_pwm_channel *pwm)
354{
355	struct bcm2835pwm_softc *sc = pwm->sc;
356
357	return sc->sc_iob + PWM_FIFO;
358}
359
360