1/* $NetBSD: meson_wdt.c,v 1.2 2021/01/27 03:10:18 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: meson_wdt.c,v 1.2 2021/01/27 03:10:18 thorpej Exp $");
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/cpu.h>
35#include <sys/device.h>
36#include <sys/wdog.h>
37
38#include <dev/sysmon/sysmonvar.h>
39
40#include <dev/fdt/fdtvar.h>
41
42#define	CBUS_REG(x)		((x) << 2)
43
44#define	WATCHDOG_TC_REG		CBUS_REG(0)
45#define	 WATCHDOG_TC_CPUS	__BITS(27,24)
46#define	 WATCHDOG_TC_ENABLE	__BIT(19)
47#define	 WATCHDOG_TC_TCNT	__BITS(15,0)
48
49#define	WATCHDOG_RESET_REG	CBUS_REG(1)
50#define	 WATCHDOG_RESET_COUNT	__BITS(15,0)
51
52#define	WATCHDOG_PERIOD_DEFAULT		8
53#define	WATCHDOG_PERIOD_MAX		8
54#define	WATCHDOG_TICKS_PER_SEC		7812
55
56static const struct device_compatible_entry compat_data[] = {
57	{ .compat = "amlogic,meson8b-wdt" },
58	DEVICE_COMPAT_EOL
59};
60
61struct meson_wdt_softc {
62	device_t		sc_dev;
63	bus_space_tag_t		sc_bst;
64	bus_space_handle_t	sc_bsh;
65
66	struct sysmon_wdog	sc_wdog;
67};
68
69#define	WDT_READ(sc, reg)		\
70	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
71#define	WDT_WRITE(sc, reg, val)	\
72	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
73
74static int
75meson_wdt_setmode(struct sysmon_wdog *smw)
76{
77	struct meson_wdt_softc * const sc = smw->smw_cookie;
78	uint32_t val;
79
80	if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
81		WDT_WRITE(sc, WATCHDOG_RESET_REG, 0);
82		val = WDT_READ(sc, WATCHDOG_TC_REG);
83		val &= ~WATCHDOG_TC_ENABLE;
84		WDT_WRITE(sc, WATCHDOG_TC_REG, val);
85		return 0;
86	}
87
88	if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
89		sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
90	} else if (smw->smw_period == 0 ||
91		   smw->smw_period > WATCHDOG_PERIOD_MAX) {
92		return EINVAL;
93	} else {
94		sc->sc_wdog.smw_period = smw->smw_period;
95	}
96
97	const u_int tcnt = sc->sc_wdog.smw_period * WATCHDOG_TICKS_PER_SEC;
98	WDT_WRITE(sc, WATCHDOG_RESET_REG, 0);
99	WDT_WRITE(sc, WATCHDOG_TC_REG, WATCHDOG_TC_CPUS | WATCHDOG_TC_ENABLE |
100	    __SHIFTIN(tcnt, WATCHDOG_TC_TCNT));
101
102	return 0;
103}
104
105static int
106meson_wdt_tickle(struct sysmon_wdog *smw)
107{
108	struct meson_wdt_softc * const sc = smw->smw_cookie;
109
110	WDT_WRITE(sc, WATCHDOG_RESET_REG, 0);
111
112	return 0;
113}
114
115static int
116meson_wdt_match(device_t parent, cfdata_t cf, void *aux)
117{
118	struct fdt_attach_args * const faa = aux;
119
120	return of_compatible_match(faa->faa_phandle, compat_data);
121}
122
123static void
124meson_wdt_attach(device_t parent, device_t self, void *aux)
125{
126	struct meson_wdt_softc * const sc = device_private(self);
127	struct fdt_attach_args * const faa = aux;
128	const int phandle = faa->faa_phandle;
129	bus_addr_t addr;
130	bus_size_t size;
131	uint32_t val;
132
133	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
134		aprint_error(": couldn't get registers\n");
135		return;
136	}
137
138	sc->sc_dev = self;
139	sc->sc_bst = faa->faa_bst;
140	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
141		aprint_error(": couldn't map registers\n");
142		return;
143	}
144
145	aprint_naive("\n");
146	aprint_normal(": EE-watchdog\n");
147
148	/* Disable watchdog */
149	WDT_WRITE(sc, WATCHDOG_RESET_REG, 0);
150	val = WDT_READ(sc, WATCHDOG_TC_REG);
151	val &= ~WATCHDOG_TC_ENABLE;
152	WDT_WRITE(sc, WATCHDOG_TC_REG, val);
153
154	/* Register watchdog */
155	sc->sc_wdog.smw_name = "EE-watchdog";
156	sc->sc_wdog.smw_setmode = meson_wdt_setmode;
157	sc->sc_wdog.smw_tickle = meson_wdt_tickle;
158	sc->sc_wdog.smw_period = WATCHDOG_PERIOD_DEFAULT;
159	sc->sc_wdog.smw_cookie = sc;
160	sysmon_wdog_register(&sc->sc_wdog);
161}
162
163CFATTACH_DECL_NEW(meson_wdt, sizeof(struct meson_wdt_softc),
164    meson_wdt_match, meson_wdt_attach, NULL, NULL);
165