1//Original:/proj/frio/dv/testcases/seq/se_excpt_ifprotviol/se_excpt_ifprotviol.dsp
2// Description: EXCPT instruction and IF Prot Viol priority
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10include(gen_int.inc)
11include(selfcheck.inc)
12include(std.inc)
13include(mmrs.inc)
14include(symtable.inc)
15
16#ifndef STACKSIZE
17#define STACKSIZE 0x100   // change for how much stack you need
18#endif
19#ifndef ITABLE
20#define ITABLE 0xF0000000
21#endif
22
23GEN_INT_INIT(ITABLE) // set location for interrupt table
24
25//
26// Reset/Bootstrap Code
27//   (Here we should set the processor operating modes, initialize registers,
28//    etc.)
29//
30
31BOOT:
32INIT_R_REGS(0);     // initialize general purpose regs
33
34INIT_P_REGS(0);     // initialize the pointers
35
36INIT_I_REGS(0);     // initialize the dsp address regs
37INIT_M_REGS(0);
38INIT_L_REGS(0);
39INIT_B_REGS(0);
40
41CLI R1;           // inhibit events during MMR writes
42
43LD32_LABEL(sp, USTACK);   // setup the user stack pointer
44USP = SP;
45
46LD32_LABEL(sp, KSTACK);   // setup the kernel stack pointer
47FP = SP;        // and frame pointer
48
49LD32(p0, EVT0);      // Setup Event Vectors and Handlers
50
51    P0 += 4;            // EVT0 not used (Emulation)
52
53    P0 += 4;            // EVT1 not used (Reset)
54
55LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
56    [ P0 ++ ] = R0;
57
58LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
59    [ P0 ++ ] = R0;
60
61    P0 += 4;            // EVT4 not used (Global Interrupt Enable)
62
63LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
64    [ P0 ++ ] = R0;
65
66LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
67    [ P0 ++ ] = R0;
68
69LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
70    [ P0 ++ ] = R0;
71
72LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
73    [ P0 ++ ] = R0;
74
75LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
76    [ P0 ++ ] = R0;
77
78LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
79    [ P0 ++ ] = R0;
80
81LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
82    [ P0 ++ ] = R0;
83
84LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
85    [ P0 ++ ] = R0;
86
87LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
88    [ P0 ++ ] = R0;
89
90LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
91    [ P0 ++ ] = R0;
92
93LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
94    [ P0 ++ ] = R0;
95
96LD32(p0, EVT_OVERRIDE);
97    R0 = 0;
98    [ P0 ++ ] = R0;
99
100    R1 = -1;     // Change this to mask interrupts (*)
101CSYNC;       // wait for MMR writes to finish
102STI R1;      // sync and reenable events (implicit write to IMASK)
103
104DUMMY:
105
106    R0 = 0 (Z);
107
108LT0 = r0;       // set loop counters to something deterministic
109LB0 = r0;
110LC0 = r0;
111LT1 = r0;
112LB1 = r0;
113LC1 = r0;
114
115ASTAT = r0;     // reset other internal regs
116SYSCFG = r0;
117RETS = r0;      // prevent X's breaking LINK instruction
118
119RETI = r0;      // prevent Xs later on
120RETX = r0;
121RETN = r0;
122RETE = r0;
123
124
125// The following code sets up the test for running in USER mode
126
127LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
128                        // ReturnFromInterrupt (RTI)
129RETI = r0;      // We need to load the return address
130
131// Comment the following line for a USER Mode test
132
133//    JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
134
135RTI;
136
137STARTSUP:
138LD32_LABEL(p1, BEGIN);
139
140LD32(p0, EVT15);
141
142CLI R1;   // inhibit events during write to MMR
143    [ P0 ] = P1;  // IVG15 (General) handler (Int 15) load with start
144CSYNC;      // wait for it
145STI R1;     // reenable events with proper imask
146
147RAISE 15;       // after we RTI, INT 15 should be taken
148
149RTI;
150
151//
152// The Main Program
153//
154
155STARTUSER:
156
157LD32_LABEL(sp, USTACK);   // setup the user stack pointer
158FP = SP;
159LINK 0;     // change for how much stack frame space you need.
160
161JUMP BEGIN;
162
163//*********************************************************************
164
165BEGIN:
166
167                // COMMENT the following line for USER MODE tests
168//    [--sp] = RETI;  // enable interrupts in supervisor mode
169
170    R0 = 0;
171    R1 = -1;
172
173
174EXCPT 2;    // the RAISE should not prevent the EXCPT from being taken
175RAISE 15;
176
177CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
178
179CHECKREG(r5, 2); // check the flag
180
181END:
182dbg_pass;            // End the test
183
184//*********************************************************************
185
186//
187// Handlers for Events
188//
189
190NHANDLE:            // NMI Handler 2
191RTN;
192
193XHANDLE:            // Exception Handler 3
194
195    [ -- SP ] = ASTAT; // save what we damage
196    [ -- SP ] = ( R7:6 );
197    R7 = SEQSTAT;
198    R7 <<= 26;
199    R7 >>= 26;      // only want EXCAUSE
200    R6 = 0x02;      // EXCAUSE 0x02 means EXCPT 2 instruction
201CC = r7 == r6;
202IF CC JUMP EXCPT2;
203
204    R6 = 0x2E;      // EXCAUSE 0x2E means Illegal Use Supervisor Resource
205CC = r7 == r6;
206IF CC JUMP IFPROTVIOL;
207
208JUMP.S OUT;       // if the EXCAUSE is wrong the test will infinite loop
209
210EXCPT2:
211    R5 = 1;         // Set a Flag
212JUMP.S OUT;
213
214IFPROTVIOL:
215    R7 = RETX;      // Fix up return address
216
217    R7 += 2;        // skip offending 16 bit instruction
218
219RETX = r7;      // and put back in RETX
220
221    R5 <<= 1;        // Alter Global Flag
222
223OUT:
224    ( R7:6 ) = [ SP ++ ];
225ASTAT = [sp++];
226RTX;
227
228HWHANDLE:           // HW Error Handler 5
229RTI;
230
231THANDLE:            // Timer Handler 6
232RTI;
233
234I7HANDLE:           // IVG 7 Handler
235RTI;
236
237I8HANDLE:           // IVG 8 Handler
238RTI;
239
240I9HANDLE:           // IVG 9 Handler
241RTI;
242
243I10HANDLE:          // IVG 10 Handler
244RTI;
245
246I11HANDLE:          // IVG 11 Handler
247RTI;
248
249I12HANDLE:          // IVG 12 Handler
250RTI;
251
252I13HANDLE:          // IVG 13 Handler
253RTI;
254
255I14HANDLE:          // IVG 14 Handler
256RTI;
257
258I15HANDLE:          // IVG 15 Handler
259RTI;
260
261
262    // padding for the icache
263
264EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
265
266//
267// Data Segment
268//
269
270.data
271DATA:
272    .space (0x10);
273
274// Stack Segments (Both Kernel and User)
275
276    .space (STACKSIZE);
277KSTACK:
278
279    .space (STACKSIZE);
280USTACK:
281