1//Original:/proj/frio/dv/testcases/seq/se_excpt_dagprotviol/se_excpt_dagprotviol.dsp 2// Description: EXCPT instruction combined with DAG Misaligned Access 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10include(gen_int.inc) 11include(selfcheck.inc) 12include(std.inc) 13include(mmrs.inc) 14include(symtable.inc) 15 16#ifndef STACKSIZE 17#define STACKSIZE 0x100 // change for how much stack you need 18#endif 19#ifndef ITABLE 20#define ITABLE 0xF0000000 21#endif 22 23GEN_INT_INIT(ITABLE) // set location for interrupt table 24 25// 26// Reset/Bootstrap Code 27// (Here we should set the processor operating modes, initialize registers, 28// etc.) 29// 30 31BOOT: 32INIT_R_REGS(0); // initialize general purpose regs 33 34INIT_P_REGS(0); // initialize the pointers 35 36INIT_I_REGS(0); // initialize the dsp address regs 37INIT_M_REGS(0); 38INIT_L_REGS(0); 39INIT_B_REGS(0); 40 41CLI R1; // inhibit events during MMR writes 42 43LD32_LABEL(sp, USTACK); // setup the user stack pointer 44USP = SP; 45 46LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer 47FP = SP; // and frame pointer 48 49LD32(p0, EVT0); // Setup Event Vectors and Handlers 50 51 P0 += 4; // EVT0 not used (Emulation) 52 53 P0 += 4; // EVT1 not used (Reset) 54 55LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 56 [ P0 ++ ] = R0; 57 58LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 59 [ P0 ++ ] = R0; 60 61 P0 += 4; // EVT4 not used (Global Interrupt Enable) 62 63LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 64 [ P0 ++ ] = R0; 65 66LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 67 [ P0 ++ ] = R0; 68 69LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 70 [ P0 ++ ] = R0; 71 72LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 73 [ P0 ++ ] = R0; 74 75LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 76 [ P0 ++ ] = R0; 77 78LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 79 [ P0 ++ ] = R0; 80 81LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 82 [ P0 ++ ] = R0; 83 84LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 85 [ P0 ++ ] = R0; 86 87LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 88 [ P0 ++ ] = R0; 89 90LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 91 [ P0 ++ ] = R0; 92 93LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 94 [ P0 ++ ] = R0; 95 96LD32(p0, EVT_OVERRIDE); 97 R0 = 0; 98 [ P0 ++ ] = R0; 99 100 R1 = -1; // Change this to mask interrupts (*) 101CSYNC; // wait for MMR writes to finish 102STI R1; // sync and reenable events (implicit write to IMASK) 103 104DUMMY: 105 106 R0 = 0 (Z); 107 108LT0 = r0; // set loop counters to something deterministic 109LB0 = r0; 110LC0 = r0; 111LT1 = r0; 112LB1 = r0; 113LC1 = r0; 114 115ASTAT = r0; // reset other internal regs 116SYSCFG = r0; 117RETS = r0; // prevent X's breaking LINK instruction 118 119RETI = r0; // prevent Xs later on 120RETX = r0; 121RETN = r0; 122RETE = r0; 123 124 125// The following code sets up the test for running in USER mode 126 127LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 128 // ReturnFromInterrupt (RTI) 129RETI = r0; // We need to load the return address 130 131// Comment the following line for a USER Mode test 132 133// JUMP STARTSUP; // jump to code start for SUPERVISOR mode 134 135RTI; 136 137STARTSUP: 138LD32_LABEL(p1, BEGIN); 139 140LD32(p0, EVT15); 141 142CLI R1; // inhibit events during write to MMR 143 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 144CSYNC; // wait for it 145STI R1; // reenable events with proper imask 146 147RAISE 15; // after we RTI, INT 15 should be taken 148 149RTI; 150 151// 152// The Main Program 153// 154 155STARTUSER: 156 157LD32_LABEL(sp, USTACK); // setup the user stack pointer 158FP = SP; 159LINK 0; // change for how much stack frame space you need. 160 161JUMP BEGIN; 162 163//********************************************************************* 164 165BEGIN: 166 167 // COMMENT the following line for USER MODE tests 168// [--sp] = RETI; // enable interrupts in supervisor mode 169 170 R0 = 0; 171 R1 = -1; 172LD32_LABEL(p1, USTACK); 173 P1 += 1; // misalign it 174 175EXCPT 2; // the RAISE should not prevent the EXCPT from being taken 176 R2 = [ P1 ]; 177 178CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); 179 180CHECKREG(r5, 2); // check the flag 181 182END: 183dbg_pass; // End the test 184 185//********************************************************************* 186 187// 188// Handlers for Events 189// 190 191NHANDLE: // NMI Handler 2 192RTN; 193 194XHANDLE: // Exception Handler 3 195 196 [ -- SP ] = ASTAT; // save what we damage 197 [ -- SP ] = ( R7:6 ); 198 R7 = SEQSTAT; 199 R7 <<= 26; 200 R7 >>= 26; // only want EXCAUSE 201 R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction 202CC = r7 == r6; 203IF CC JUMP EXCPT2; 204 205 R6 = 0x24; // EXCAUSE 0x24 means DAG misalign 206CC = r7 == r6; 207IF CC JUMP DGPROTVIOL; 208 209JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop 210 211EXCPT2: 212 R5 = 1; // Set a Flag 213JUMP.S OUT; 214 215DGPROTVIOL: 216 R7 = RETX; // Fix up return address 217 218 R7 += 2; // skip offending 16 bit instruction 219 220RETX = r7; // and put back in RETX 221 222 R5 <<= 1; // Alter Global Flag 223 224OUT: 225 ( R7:6 ) = [ SP ++ ]; 226ASTAT = [sp++]; 227RTX; 228 229HWHANDLE: // HW Error Handler 5 230RTI; 231 232THANDLE: // Timer Handler 6 233RTI; 234 235I7HANDLE: // IVG 7 Handler 236RTI; 237 238I8HANDLE: // IVG 8 Handler 239RTI; 240 241I9HANDLE: // IVG 9 Handler 242RTI; 243 244I10HANDLE: // IVG 10 Handler 245RTI; 246 247I11HANDLE: // IVG 11 Handler 248RTI; 249 250I12HANDLE: // IVG 12 Handler 251RTI; 252 253I13HANDLE: // IVG 13 Handler 254RTI; 255 256I14HANDLE: // IVG 14 Handler 257RTI; 258 259I15HANDLE: // IVG 15 Handler 260RTI; 261 262 263 // padding for the icache 264 265EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; 266 267// 268// Data Segment 269// 270 271.data 272DATA: 273 .space (0x10); 274 275// Stack Segments (Both Kernel and User) 276 277 .space (STACKSIZE); 278KSTACK: 279 280 .space (STACKSIZE); 281USTACK: 282