1//Original:/proj/frio/dv/testcases/debug/dbg_tr_simplejp/dbg_tr_simplejp.dsp 2// Description: This test performs simple jumps and verifies the trace buffer 3// recording for simple jumps. 4# mach: bfin 5# sim: --environment operating 6 7#include "test.h" 8.include "testutils.inc" 9start 10 11include(std.inc) 12include(mmrs.inc) 13include(selfcheck.inc) 14include(symtable.inc) 15 16#ifndef ITABLE 17#define ITABLE CODE_ADDR_1 // 18#endif 19 20// This test embeds .text offsets, so pad our test so it lines up. 21.space 0x5e 22 23// Boot code 24 25 BOOT : 26INIT_R_REGS(0); // Initialize Dregs 27INIT_P_REGS(0); // Initialize Pregs 28 29CHECK_INIT_DEF(p5); // CHECK_INIT(p5, 0x00BFFFFC); 30 31LD32(p0, EVT0); // Setup Event Vectors and Handlers 32 33LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 34 [ P0 ++ ] = R0; 35 36LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 37 [ P0 ++ ] = R0; 38 39LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 40 [ P0 ++ ] = R0; 41 42LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 43 [ P0 ++ ] = R0; 44 45 [ P0 ++ ] = R0; // IVT4 not used 46 47LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 48 [ P0 ++ ] = R0; 49 50LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 51 [ P0 ++ ] = R0; 52 53LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 54 [ P0 ++ ] = R0; 55 56LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 57 [ P0 ++ ] = R0; 58 59LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 60 [ P0 ++ ] = R0; 61 62LD32_LABEL(r0, I10HANDLE); // IVG10 Handler 63 [ P0 ++ ] = R0; 64 65LD32_LABEL(r0, I11HANDLE); // IVG11 Handler 66 [ P0 ++ ] = R0; 67 68LD32_LABEL(r0, I12HANDLE); // IVG12 Handler 69 [ P0 ++ ] = R0; 70 71LD32_LABEL(r0, I13HANDLE); // IVG13 Handler 72 [ P0 ++ ] = R0; 73 74LD32_LABEL(r0, I14HANDLE); // IVG14 Handler 75 [ P0 ++ ] = R0; 76 77LD32_LABEL(r0, I15HANDLE); // IVG15 Handler 78 [ P0 ++ ] = R0; 79 80LD32(p0, EVT_OVERRIDE); 81 R0 = 0; 82 [ P0 ++ ] = R0; 83 R0 = -1; // Change this to mask interrupts (*) 84 [ P0 ] = R0; // IMASK 85 86LD32_LABEL(p1, START); 87 88LD32(p0, EVT15); 89 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 90 91LD32_LABEL(r7, DUMMY); 92RETI = r7; 93RAISE 15; // after we RTI, INT 15 should be taken 94 95NOP; // Workaround for Bug 217 96RTI; 97NOP; 98NOP; 99NOP; 100DUMMY: 101 NOP; 102NOP; 103NOP; 104NOP; 105 106 107 108 START : 109WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer 110 // TBUFPWR = 1 111 // TBUFEN = 1 112 // TBUFOVF = 0 113 // CMPLP = 0 114NOP; 115NOP; 116NOP; 117NOP; 118NOP; 119NOP; 120NOP; 121NOP; 122NOP; 123JUMP.S label1; // 0x0224 124 R4.L = 0x1111; // Will be killed 125 R4.H = 0x1111; // Will be killed 126NOP; 127NOP; 128NOP; 129label2: R5.H = 0x7777; // 0x0234 130 R5.L = 0x7888; 131JUMP.S label3; //0x023c 132 R6.L = 0x1111; // Will be killed 133 R6.H = 0x1111; // Will be killed 134NOP; 135NOP; 136NOP; 137NOP; 138NOP; 139label1: R4.H = 0x5555; // 0x0250 140 R4.L = 0x6666; 141NOP; 142JUMP.S label2; // 0x0258 143 R5.L = 0x1111; // Will be killed 144 R5.H = 0x1111; // Will be killed 145NOP; 146NOP; 147NOP; 148NOP; 149label3: R6.H = 0x7999; //0x026c 150 R6.L = 0x7aaa; 151NOP; 152NOP; 153NOP; 154NOP; 155 156WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer 157 158NOP; 159NOP; 160NOP; 161NOP; 162NOP; 163 // Read the contents of the Trace Buffer 164 165RD_MMR(TBUFSTAT, p0, r2); 166CHECKREG(r2, 0x00000003); 167 168 // Read 3rd Entry of the Trace Buffer 169RD_MMR(TBUF, p0, r0); 170CHECKREG(r0, 0x0000026c); 171 172RD_MMR(TBUFSTAT, p0, r2); 173CHECKREG(r2, 0x00000003); 174 175RD_MMR(TBUF, p0, r1); 176CHECKREG(r1, 0x0000023c); 177 178RD_MMR(TBUFSTAT, p0, r2); 179CHECKREG(r2, 0x00000002); 180 181 // Read 2nd Entry of the Trace Buffer 182RD_MMR(TBUF, p0, r0); 183CHECKREG(r0, 0x00000234); 184 185RD_MMR(TBUFSTAT, p0, r2); 186CHECKREG(r2, 0x00000002); 187 188RD_MMR(TBUF, p0, r1); 189CHECKREG(r1, 0x0000025a); 190 191RD_MMR(TBUFSTAT, p0, r2); 192CHECKREG(r2, 0x00000001); 193 194 // Read ist Entry of the Trace Buffer 195RD_MMR(TBUF, p0, r0); 196CHECKREG(r0, 0x00000250); 197 198RD_MMR(TBUFSTAT, p0, r2); 199CHECKREG(r2, 0x00000001); 200 201RD_MMR(TBUF, p0, r1); 202CHECKREG(r1, 0x00000224); 203 204RD_MMR(TBUFSTAT, p0, r2); 205CHECKREG(r2, 0x00000000); 206 207WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power 208 209NOP; 210NOP; 211NOP; 212NOP; 213NOP; 214NOP; 215dbg_pass; // Call Endtest Macro 216 217 218 219//********************************************************************* 220// 221// Handlers for Events 222// 223 224EHANDLE: // Emulation Handler 0 225RTE; 226 227RHANDLE: // Reset Handler 1 228RTI; 229 230NHANDLE: // NMI Handler 2 231RTN; 232 233XHANDLE: // Exception Handler 3 234RTX; 235 236HWHANDLE: // HW Error Handler 5 237RTI; 238 239THANDLE: // Timer Handler 6 240RTI; 241 242I7HANDLE: // IVG 7 Handler 243RTI; 244 245I8HANDLE: // IVG 8 Handler 246RTI; 247 248I9HANDLE: // IVG 9 Handler 249RTI; 250 251I10HANDLE: // IVG 10 Handler 252RTI; 253 254I11HANDLE: // IVG 11 Handler 255RTI; 256 257I12HANDLE: // IVG 12 Handler 258RTI; 259 260I13HANDLE: // IVG 13 Handler 261RTI; 262 263I14HANDLE: // IVG 14 Handler 264RTI; 265 266I15HANDLE: // IVG 15 Handler 267RTI; 268