1//Original:/proj/frio/dv/testcases/core/c_seq_wb_rtn_lsmmrj_mvp/c_seq_wb_rtn_lsmmrj_mvp.dsp 2// Spec Reference: sequencer:wb ( rtn ldst mmr jump regmv pushpopmultiple) 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10include(std.inc) 11include(selfcheck.inc) 12include(gen_int.inc) 13INIT_R_REGS(0); 14INIT_P_REGS(0); 15INIT_I_REGS(0); // initialize the dsp address regs 16INIT_M_REGS(0); 17INIT_L_REGS(0); 18INIT_B_REGS(0); 19//CHECK_INIT(p5, 0xe0000000); 20include(symtable.inc) 21CHECK_INIT_DEF(p5); 22 23#ifndef STACKSIZE 24#define STACKSIZE 0x10 25#endif 26#ifndef EVT 27#define EVT 0xFFE02000 28#endif 29#ifndef EVT15 30#define EVT15 0xFFE0203C 31#endif 32#ifndef EVT_OVERRIDE 33#define EVT_OVERRIDE 0xFFE02100 34#endif 35#ifndef ITABLE 36#define ITABLE DATA_ADDR_1 37#endif 38 39GEN_INT_INIT(ITABLE) // set location for interrupt table 40 41// 42// Reset/Bootstrap Code 43// (Here we should set the processor operating modes, initialize registers, 44// 45 46BOOT: 47 48 // in reset mode now 49LD32_LABEL(sp, KSTACK); // setup the stack pointer 50FP = SP; // and frame pointer 51 52LD32(p0, EVT); // Setup Event Vectors and Handlers 53LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 54 [ P0 ++ ] = R0; 55 56LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 57 [ P0 ++ ] = R0; 58 59LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 60 [ P0 ++ ] = R0; 61 62LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 63 [ P0 ++ ] = R0; 64 65 [ P0 ++ ] = R0; // IVT4 not used 66 67LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 68 [ P0 ++ ] = R0; 69 70LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 71 [ P0 ++ ] = R0; 72 73LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 74 [ P0 ++ ] = R0; 75 76LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 77 [ P0 ++ ] = R0; 78 79LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 80 [ P0 ++ ] = R0; 81 82LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 83 [ P0 ++ ] = R0; 84 85LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 86 [ P0 ++ ] = R0; 87 88LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 89 [ P0 ++ ] = R0; 90 91LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 92 [ P0 ++ ] = R0; 93 94LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 95 [ P0 ++ ] = R0; 96 97LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 98 [ P0 ++ ] = R0; 99 100LD32(p0, EVT_OVERRIDE); 101 R0 = 0; 102 [ P0 ++ ] = R0; 103 R0 = -1; // Change this to mask interrupts (*) 104 [ P0 ] = R0; // IMASK 105CSYNC; 106 107DUMMY: 108 109 R0 = 0 (Z); 110 111LT0 = r0; // set loop counters to something deterministic 112LB0 = r0; 113LC0 = r0; 114LT1 = r0; 115LB1 = r0; 116LC1 = r0; 117 118ASTAT = r0; // reset other internal regs 119 120// The following code sets up the test for running in USER mode 121 122LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 123 // ReturnFromInterrupt (RTI) 124RETI = r0; // We need to load the return address 125 126// Comment the following line for a USER Mode test 127 128JUMP STARTSUP; // jump to code start for SUPERVISOR mode 129 130RTI; 131 132STARTSUP: 133LD32_LABEL(p1, BEGIN); 134 135LD32(p0, EVT15); 136 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 137 138RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in 139 // SUPERVISOR MODE & go to different RAISE in supervisor mode 140 // until the end of the test. 141 142NOP; // Workaround for Bug 217 143RTI; 144 145// 146// The Main Program 147// 148STARTUSER: 149LD32_LABEL(sp, USTACK); // setup the stack pointer 150FP = SP; // set frame pointer 151JUMP BEGIN; 152 153//********************************************************************* 154 155BEGIN: 156 157 // COMMENT the following line for USER MODE tests 158 [ -- SP ] = RETI; // enable interrupts in supervisor mode 159 160 // **** YOUR CODE GOES HERE **** 161 162 163 164 // PUT YOUR TEST HERE! 165// PUSH 166LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 167//LD32(p2, DATA_ADDR_1); 168loadsym P2, DATA; 169LD32(p3, 0xab5fd490); 170LD32(p4, 0xa581bd94); 171 172LD32(r2, 0x14789232); 173 [ P1 ] = R2; 174 R0 = 0x01; 175 R1 = 0x02; 176 R2 = 0x03; 177 R3 = 0x04; 178 R4 = 0x05; 179 R5 = 0x06; 180 R6 = 0x07; 181 R7 = 0x08; 182 [ -- SP ] = ( R7:0 ); 183RAISE 2; // RTN 184 R0 = [ P2 ++ ]; 185 R1 = [ P1 ]; 186JUMP.S LABEL1; 187 P3 = R7; 188 R4 = P3; 189 [ -- SP ] = ( R7:0 ); 190 R1 = 0x12; 191 R2 = 0x13; 192 R3 = 0x14; 193 R4 = 0x15; 194 R5 = 0x16; 195 R6 = 0x17; 196 R7 = 0x18; 197 198LABEL1: 199RAISE 5; // RTI 200 R2 = [ P2 ++ ]; 201 202 P4 = R6; 203 R3 = P4; 204 205 [ -- SP ] = ( R7:0 ); 206 207 R2 = 0x23; 208 R3 = 0x24; 209 R4 = 0x25; 210 R5 = 0x26; 211 R6 = 0x27; 212 R7 = 0x28; 213 214// wrt-rd EVT5 = 0xFFE02034 215LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 216RAISE 6; // RTI 217 R4 = [ P2 ++ ]; 218 R6 = [ P1 ]; 219JUMP.S LABEL2; 220 P3 = R3; 221 R5 = P3; 222 [ -- SP ] = ( R7:0 ); 223// POP 224 R0 = 0x00; 225 R1 = 0x00; 226 R2 = 0x00; 227 R3 = 0x00; 228 R4 = 0x00; 229 R5 = 0x00; 230 R6 = 0x00; 231 R7 = 0x00; 232 233LABEL2: 234CSYNC; 235CHECKREG(r0, 0x00010203); 236CHECKREG(r1, 0x14789232); 237CHECKREG(r2, 0x00000023); 238CHECKREG(r3, 0x00000024); 239CHECKREG(r4, 0x08090A0B); 240CHECKREG(r5, 0x00000026); 241CHECKREG(r6, 0x14789232); 242RAISE 7; // RTI 243 R0 = [ P2 ++ ]; 244 R1 = [ P1 ]; 245 P4 = R4; 246 R2 = P4; 247 ( R7:0 ) = [ SP ++ ]; 248 249 250 251CHECKREG(r0, 0x00010203); 252CHECKREG(r1, 0x14789232); 253CHECKREG(r2, 0x04050607); 254CHECKREG(r3, 0x00000007); 255CHECKREG(r4, 0x00000005); 256CHECKREG(r5, 0x00000006); 257CHECKREG(r6, 0x00000007); 258CHECKREG(r7, 0x00000008); 259// wrt-rd EVT13 = 0xFFE02034 260LD32(p1, 0xFFE02034); 261RAISE 8; // RTI 262 R0 = [ P2 ++ ]; 263 R1 = [ P1 ]; 264JUMP.S LABEL3; 265 P1 = R5; 266 R6 = P1; 267 ( R7:0 ) = [ SP ++ ]; 268//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped 269//CHECKREG(r1, 0x000000b2); // so they cannot appear here 270//CHECKREG(r2, 0x000000c3); 271//CHECKREG(r3, 0x000000d4); 272//CHECKREG(r4, 0x000000e5); 273//CHECKREG(r5, 0x000000f6); 274//CHECKREG(r6, 0x00000017); 275//CHECKREG(r7, 0x00000028); 276 R0 = 12; 277 R1 = 13; 278 R2 = 14; 279 R3 = 15; 280 R4 = 16; 281 R5 = 17; 282 R6 = 18; 283 R7 = 19; 284 285 286LABEL3: 287CSYNC; 288CHECKREG(r0, 0x10111213); 289CHECKREG(r1, 0x14789232); 290RAISE 9; // RTI 291 P3 = R6; 292 R7 = P3; 293 ( R7:0 ) = [ SP ++ ]; 294 295CHECKREG(r0, 0x00000001); 296CHECKREG(r1, 0x00000002); 297CHECKREG(r2, 0x00000003); 298CHECKREG(r3, 0x00000004); 299CHECKREG(r4, 0x00000005); 300CHECKREG(r5, 0x00000006); 301CHECKREG(r6, 0x00000007); 302CHECKREG(r7, 0x00000008); 303R0 = I0; 304R1 = I1; 305R2 = I2; 306R3 = I3; 307CHECKREG(r0, 0x00000006); 308CHECKREG(r1, 0x00000002); 309CHECKREG(r2, 0x00000002); 310CHECKREG(r3, 0x00000002); 311 312 313END: 314dbg_pass; // End the test 315 316//********************************************************************* 317 318// 319// Handlers for Events 320// 321 322EHANDLE: // Emulation Handler 0 323RTE; 324 325RHANDLE: // Reset Handler 1 326RTI; 327 328NHANDLE: // NMI Handler 2 329 I0 += 2; 330RTN; 331 // *********** 332 R0 = [ P2 ++ ]; 333 R1 = [ P1 ]; 334JUMP.S LABEL3; 335 P1 = R5; 336 R6 = P1; 337 ( R7:0 ) = [ SP ++ ]; 338 // *********** 339 340XHANDLE: // Exception Handler 3 341 R1 = 3; 342RTX; 343 344HWHANDLE: // HW Error Handler 5 345 I1 += 2; 346RTI; 347 348THANDLE: // Timer Handler 6 349 I2 += 2; 350RTI; 351 352I7HANDLE: // IVG 7 Handler 353 I3 += 2; 354RTI; 355I8HANDLE: // IVG 8 Handler 356 I0 += 2; 357RTI; 358 359I9HANDLE: // IVG 9 Handler 360 I0 += 2; 361RTI; 362 363I10HANDLE: // IVG 10 Handler 364 R7 = 10; 365RTI; 366 367I11HANDLE: // IVG 11 Handler 368 I0 = R0; 369 I1 = R1; 370 I2 = R2; 371 I3 = R3; 372 M0 = R4; 373 R0 = 11; 374RTI; 375 376I12HANDLE: // IVG 12 Handler 377 R1 = 12; 378RTI; 379 380I13HANDLE: // IVG 13 Handler 381 R2 = 13; 382RTI; 383 384I14HANDLE: // IVG 14 Handler 385 R3 = 14; 386RTI; 387 388I15HANDLE: // IVG 15 Handler 389 R4 = 15; 390RTI; 391 392NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 393 394// 395// Data Segment 396// 397 398.section MEM_DATA_ADDR_1,"aw" 399DATA: 400// .space (0x10); 401.dd 0x00010203 402.dd 0x04050607 403.dd 0x08090A0B 404.dd 0x0C0D0E0F 405.dd 0x10111213 406.dd 0x14151617 407.dd 0x18191A1B 408.dd 0x1C1D1E1F 409.dd 0x11223344 410.dd 0x55667788 411.dd 0x99717273 412.dd 0x74757677 413.dd 0x82838485 414.dd 0x86878889 415.dd 0x80818283 416.dd 0x84858687 417.dd 0x01020304 418.dd 0x05060708 419.dd 0x09101112 420.dd 0x14151617 421.dd 0x18192021 422 423 424// Stack Segments (Both Kernel and User) 425 426 .space (STACKSIZE); 427KSTACK: 428 429 .space (STACKSIZE); 430USTACK: 431 432.section MEM_DATA_ADDR_2,"aw" 433.dd 0x20212223 434.dd 0x24252627 435.dd 0x28292A2B 436.dd 0x2C2D2E2F 437.dd 0x30313233 438.dd 0x34353637 439.dd 0x38393A3B 440.dd 0x3C3D3E3F 441.dd 0x91929394 442.dd 0x95969798 443.dd 0x99A1A2A3 444.dd 0xA5A6A7A8 445.dd 0xA9B0B1B2 446.dd 0xB3B4B5B6 447.dd 0xB7B8B9C0 448