1//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmrj_mvpop/c_seq_ex2_mmrj_mvpop.dsp 2// Spec Reference: sequencer stage ex2 ( mmr + jump + regmv + pushpopmultiple) 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10include(std.inc) 11include(selfcheck.inc) 12include(gen_int.inc) 13INIT_R_REGS(0); 14INIT_P_REGS(0); 15INIT_I_REGS(0); // initialize the dsp address regs 16INIT_M_REGS(0); 17INIT_L_REGS(0); 18INIT_B_REGS(0); 19//CHECK_INIT(p5, 0xe0000000); 20include(symtable.inc) 21CHECK_INIT_DEF(p5); 22 23#ifndef STACKSIZE 24#define STACKSIZE 0x10 25#endif 26#ifndef EVT 27#define EVT 0xFFE02000 28#endif 29#ifndef EVT15 30#define EVT15 0xFFE0203C 31#endif 32#ifndef EVT_OVERRIDE 33#define EVT_OVERRIDE 0xFFE02100 34#endif 35#ifndef ITABLE 36#define ITABLE DATA_ADDR_1 37#endif 38 39GEN_INT_INIT(ITABLE) // set location for interrupt table 40 41// 42// Reset/Bootstrap Code 43// (Here we should set the processor operating modes, initialize registers, 44// 45 46BOOT: 47 48 // in reset mode now 49LD32_LABEL(sp, KSTACK); // setup the stack pointer 50FP = SP; // and frame pointer 51 52LD32(p0, EVT); // Setup Event Vectors and Handlers 53LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 54 [ P0 ++ ] = R0; 55 56LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 57 [ P0 ++ ] = R0; 58 59LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 60 [ P0 ++ ] = R0; 61 62LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 63 [ P0 ++ ] = R0; 64 65 [ P0 ++ ] = R0; // IVT4 not used 66 67LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 68 [ P0 ++ ] = R0; 69 70LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 71 [ P0 ++ ] = R0; 72 73LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 74 [ P0 ++ ] = R0; 75 76LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 77 [ P0 ++ ] = R0; 78 79LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 80 [ P0 ++ ] = R0; 81 82LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 83 [ P0 ++ ] = R0; 84 85LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 86 [ P0 ++ ] = R0; 87 88LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 89 [ P0 ++ ] = R0; 90 91LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 92 [ P0 ++ ] = R0; 93 94LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 95 [ P0 ++ ] = R0; 96 97LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 98 [ P0 ++ ] = R0; 99 100LD32(p0, EVT_OVERRIDE); 101 R0 = 0; 102 [ P0 ++ ] = R0; 103 R0 = -1; // Change this to mask interrupts (*) 104 [ P0 ] = R0; // IMASK 105CSYNC; 106 107DUMMY: 108 109 R0 = 0 (Z); 110 111LT0 = r0; // set loop counters to something deterministic 112LB0 = r0; 113LC0 = r0; 114LT1 = r0; 115LB1 = r0; 116LC1 = r0; 117 118ASTAT = r0; // reset other internal regs 119 120// The following code sets up the test for running in USER mode 121 122LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 123 // ReturnFromInterrupt (RTI) 124RETI = r0; // We need to load the return address 125 126// Comment the following line for a USER Mode test 127 128JUMP STARTSUP; // jump to code start for SUPERVISOR mode 129 130RTI; 131 132STARTSUP: 133LD32_LABEL(p1, BEGIN); 134 135LD32(p0, EVT15); 136 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 137 138RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in 139 // SUPERVISOR MODE & go to different RAISE in supervisor mode 140 // until the end of the test. 141 142NOP; // Workaround for Bug 217 143RTI; 144 145// 146// The Main Program 147// 148STARTUSER: 149LD32_LABEL(sp, USTACK); // setup the stack pointer 150FP = SP; // set frame pointer 151JUMP BEGIN; 152 153//********************************************************************* 154 155BEGIN: 156 157 // COMMENT the following line for USER MODE tests 158 [ -- SP ] = RETI; // enable interrupts in supervisor mode 159 160 // **** YOUR CODE GOES HERE **** 161 162 163 164 // PUT YOUR TEST HERE! 165// PUSH 166LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 167LD32(p2, DATA_ADDR_1); 168LD32(p3, 0xab5fd490); 169LD32(p4, 0xa581bd94); 170 171LD32(r2, 0x14789232); 172 [ P1 ] = R2; 173CSYNC; 174 R0 = 0x01; 175 R1 = 0x02; 176 R2 = 0x03; 177 R3 = 0x04; 178 R4 = 0x05; 179 R5 = 0x06; 180 R6 = 0x07; 181 R7 = 0x08; 182 183 [ -- SP ] = ( R7:0 ); 184// RAISE 2; // RTN 185 [ P1 ] = R0; 186JUMP.S LABEL1; 187 P1 = R1; 188 R2 = P1; 189 [ -- SP ] = ( R7:0 ); 190 R1 = 0x12; 191 R2 = 0x13; 192 R3 = 0x14; 193 R4 = 0x15; 194 R5 = 0x16; 195 R6 = 0x17; 196 R7 = 0x18; 197 198LABEL1: 199// RAISE 5; // RTI 200 P2 = R2; 201 R3 = P2; 202 203 [ -- SP ] = ( R7:0 ); 204 205 R2 = 0x23; 206 R3 = 0x24; 207 R4 = 0x25; 208 R5 = 0x26; 209 R6 = 0x27; 210 R7 = 0x28; 211 212// wrt-rd EVT5 = 0xFFE02034 213LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 214// RAISE 6; // RTI 215 R0 = [ P1 ]; 216JUMP.S LABEL2; 217 P3 = R3; 218 R4 = P3; 219 [ -- SP ] = ( R7:0 ); 220// POP 221 R0 = 0x00; 222 R1 = 0x00; 223 R2 = 0x00; 224 R3 = 0x00; 225 R4 = 0x00; 226 R5 = 0x00; 227 R6 = 0x00; 228 R7 = 0x00; 229 230LABEL2: 231CHECKREG(r0, 0x00000001); 232// RAISE 7; // RTI 233 P4 = R4; 234 R5 = P4; 235 ( R7:0 ) = [ SP ++ ]; 236 237 238 239CHECKREG(r0, 0x00000001); 240CHECKREG(r1, 0x00000002); 241CHECKREG(r2, 0x00000003); 242CHECKREG(r3, 0x00000003); 243CHECKREG(r4, 0x00000005); 244CHECKREG(r5, 0x00000006); 245CHECKREG(r6, 0x00000007); 246CHECKREG(r7, 0x00000008); 247// wrt-rd EVT13 = 0xFFE02034 248LD32(p1, 0xFFE02034); 249// RAISE 8; // RTI 250 R0 = [ P1 ]; 251JUMP.S LABEL3; 252 P1 = R5; 253 R6 = P1; 254 ( R7:0 ) = [ SP ++ ]; 255//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped 256//CHECKREG(r1, 0x000000b2); // so they cannot appear here 257//CHECKREG(r2, 0x000000c3); 258//CHECKREG(r3, 0x000000d4); 259//CHECKREG(r4, 0x000000e5); 260//CHECKREG(r5, 0x000000f6); 261//CHECKREG(r6, 0x00000017); 262//CHECKREG(r7, 0x00000028); 263 R0 = 12; 264 R1 = 13; 265 R2 = 14; 266 R3 = 15; 267 R4 = 16; 268 R5 = 17; 269 R6 = 18; 270 R7 = 19; 271 272 273LABEL3: 274CHECKREG(r0, 0x00000001); 275// RAISE 9; // RTI 276 P2 = R6; 277 R7 = P2; 278 ( R7:0 ) = [ SP ++ ]; 279 280CHECKREG(r0, 0x00000001); 281CHECKREG(r1, 0x00000002); 282CHECKREG(r2, 0x00000003); 283CHECKREG(r3, 0x00000004); 284CHECKREG(r4, 0x00000005); 285CHECKREG(r5, 0x00000006); 286CHECKREG(r6, 0x00000007); 287CHECKREG(r7, 0x00000008); 288R0 = I0; 289R1 = I1; 290R2 = I2; 291R3 = I3; 292CHECKREG(r0, 0x00000000); 293CHECKREG(r1, 0x00000000); 294CHECKREG(r2, 0x00000000); 295CHECKREG(r3, 0x00000000); 296 297 298END: 299dbg_pass; // End the test 300 301//********************************************************************* 302 303// 304// Handlers for Events 305// 306 307EHANDLE: // Emulation Handler 0 308RTE; 309 310RHANDLE: // Reset Handler 1 311RTI; 312 313NHANDLE: // NMI Handler 2 314 I0 += 2; 315RTN; 316 317XHANDLE: // Exception Handler 3 318 R1 = 3; 319RTX; 320 321HWHANDLE: // HW Error Handler 5 322 I1 += 2; 323RTI; 324 325THANDLE: // Timer Handler 6 326 I2 += 2; 327RTI; 328 329I7HANDLE: // IVG 7 Handler 330 I3 += 2; 331RTI; 332 333I8HANDLE: // IVG 8 Handler 334 I0 += 2; 335RTI; 336 337I9HANDLE: // IVG 9 Handler 338 I0 += 2; 339RTI; 340 341I10HANDLE: // IVG 10 Handler 342 R7 = 10; 343RTI; 344 345I11HANDLE: // IVG 11 Handler 346 I0 = R0; 347 I1 = R1; 348 I2 = R2; 349 I3 = R3; 350 M0 = R4; 351 R0 = 11; 352RTI; 353 354I12HANDLE: // IVG 12 Handler 355 R1 = 12; 356RTI; 357 358I13HANDLE: // IVG 13 Handler 359 R2 = 13; 360RTI; 361 362I14HANDLE: // IVG 14 Handler 363 R3 = 14; 364RTI; 365 366I15HANDLE: // IVG 15 Handler 367 R4 = 15; 368RTI; 369 370NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 371 372// 373// Data Segment 374// 375 376.data 377DATA: 378 .space (0x10); 379 380// Stack Segments (Both Kernel and User) 381 382 .space (STACKSIZE); 383KSTACK: 384 385 .space (STACKSIZE); 386USTACK: 387