1//Original:/proj/frio/dv/testcases/core/c_mmr_loop/c_mmr_loop.dsp
2// Spec Reference: mmr loop  (interr control)  no exception
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10include(gen_int.inc)
11include(selfcheck.inc)
12include(std.inc)
13include(mmrs.inc)
14
15#ifndef STACKSIZE
16#define STACKSIZE 0x10
17#endif
18//
19
20////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
21
22//
23// Reset/Bootstrap Code
24//   (Here we set the processor operating modes, initialize registers
25//    etc.)
26//
27
28BOOT:
29
30INIT_R_REGS(0);
31INIT_P_REGS(0);
32INIT_I_REGS(0);     // initialize the dsp address regs
33INIT_M_REGS(0);
34INIT_L_REGS(0);
35INIT_B_REGS(0);
36    //CHECK_INIT(p5, 0xe0000000);
37include(symtable.inc)
38CHECK_INIT_DEF(p5);
39
40CLI R1;           // inhibit events during MMR writes
41
42LD32_LABEL(sp, USTACK);   // setup the user stack pointer
43USP = SP;                  // and frame pointer
44
45LD32_LABEL(sp, KSTACK);   // setup the stack pointer
46FP = SP;                  // and frame pointer
47
48LD32(p0, EVT0);      // Setup Event Vectors and Handlers
49LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
50    [ P0 ++ ] = R0;
51
52LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
53    [ P0 ++ ] = R0;
54
55LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
56    [ P0 ++ ] = R0;
57
58LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
59    [ P0 ++ ] = R0;
60
61    [ P0 ++ ] = R0;          // EVT4 not used global Interr Enable (INT4)
62
63LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
64    [ P0 ++ ] = R0;
65
66LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
67    [ P0 ++ ] = R0;
68
69LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
70    [ P0 ++ ] = R0;
71
72LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
73    [ P0 ++ ] = R0;
74
75LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
76    [ P0 ++ ] = R0;
77
78LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
79    [ P0 ++ ] = R0;
80
81LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
82    [ P0 ++ ] = R0;
83
84LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
85    [ P0 ++ ] = R0;
86
87LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
88    [ P0 ++ ] = R0;
89
90LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
91    [ P0 ++ ] = R0;
92
93LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
94    [ P0 ++ ] = R0;
95
96LD32(p0, EVT_OVERRIDE);
97    R0 = 0;
98    [ P0 ++ ] = R0;
99
100    R1 = -1;     // Change this to mask interrupts (*)
101CSYNC;       // wait for MMR writes to finish
102STI R1;      // sync and reenable events (implicit write to IMASK)
103
104DUMMY:
105
106    R0 = 0 (Z);
107
108LT0 = r0;       // set loop counters to something deterministic
109LB0 = r0;
110LC0 = r0;
111LT1 = r0;
112LB1 = r0;
113LC1 = r0;
114
115ASTAT = r0;     // reset other internal regs
116SYSCFG = r0;
117RETS = r0;      // prevent X's breaking LINK instruction
118
119// The following code sets up the test for running in USER mode
120
121LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
122                        // ReturnFromInterrupt (RTI)
123RETI = r0;      // We need to load the return address
124
125// Comment the following line for a USER Mode test
126
127JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
128
129RTI;
130
131STARTSUP:
132LD32_LABEL(p1, BEGIN);
133
134LD32(p0, EVT15);
135
136CLI R1;    // inhibit events during write to MMR
137    [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
138CSYNC;       // wait for it
139STI R1;      // reenable events with proper imask
140
141RAISE 15;       // after we RTI, INT 15 should be taken
142
143RTI;
144
145//
146// The Main Program
147//
148STARTUSER:
149LINK 0;     // change for how much stack frame space you need.
150
151JUMP BEGIN;
152
153
154
155//*********************************************************************
156
157BEGIN:
158
159                // COMMENT the following line for USER MODE tests
160    [ -- SP ] = RETI;  // enable interrupts in supervisor mode
161
162                // **** YOUR CODE GOES HERE ****
163// EVTx
164    // wrt-rd  EVT0: 0 bits, rw=0   = 0xFFE02000
165LD32(p0, 0xFFE02000);
166LD32(r0, 0x00000000);
167    [ P0 ] = R0;
168
169    // wrt-rd EVT1: 32 bits, rw=0   = 0xFFE02004
170LD32(p0, 0xFFE02004);
171LD32(r0, 0x00000000);
172    [ P0 ] = R0;
173
174    // wrt-rd     EVT2              = 0xFFE02008
175LD32(p0, 0xFFE02008);
176LD32(r0, 0xE1DE5D1C);
177    [ P0 ] = R0;
178
179    // wrt-rd     EVT3              = 0xFFE0200C
180LD32(p0, 0xFFE0200C);
181LD32(r0, 0x9CC20332);
182    [ P0 ] = R0;
183
184    // wrt-rd     EVT4              = 0xFFE02010
185LD32(p0, 0xFFE02010);
186LD32(r0, 0x00000000);   // not implemented
187    [ P0 ] = R0;
188
189    // wrt-rd     EVT5              = 0xFFE02014
190LD32(p0, 0xFFE02014);
191LD32(r0, 0x55552345);
192    [ P0 ] = R0;
193
194    // wrt-rd     EVT6              = 0xFFE02018
195LD32(p0, 0xFFE02018);
196LD32(r0, 0x66663456);
197    [ P0 ] = R0;
198
199    // wrt-rd     EVT7              = 0xFFE0201C
200LD32(p0, 0xFFE0201C);
201LD32(r0, 0x77774567);
202    [ P0 ] = R0;
203
204    // wrt-rd     EVT8              = 0xFFE02020
205LD32(p0, 0xFFE02020);
206LD32(r0, 0x88885678);
207    [ P0 ] = R0;
208
209    // wrt-rd     EVT9              = 0xFFE02024
210LD32(p0, 0xFFE02024);
211LD32(r0, 0x99996789);
212    [ P0 ] = R0;
213
214    // wrt-rd     EVT10             = 0xFFE02028
215LD32(p0, 0xFFE02028);
216LD32(r0, 0xaaaa1234);
217    [ P0 ] = R0;
218
219    // wrt-rd     EVT11             = 0xFFE0202C
220LD32(p0, 0xFFE0202C);
221LD32(r0, 0xBBBBABC6);
222    [ P0 ] = R0;
223
224    // wrt-rd     EVT12             = 0xFFE02030
225LD32(p0, 0xFFE02030);
226LD32(r0, 0xCCCCABC6);
227    [ P0 ] = R0;
228
229    // wrt-rd     EVT13             = 0xFFE02034
230LD32(p0, 0xFFE02034);
231LD32(r0, 0xDDDDABC6);
232    [ P0 ] = R0;
233
234    // wrt-rd     EVT14             = 0xFFE02038
235LD32(p0, 0xFFE02038);
236LD32(r0, 0xEEEEABC6);
237    [ P0 ] = R0;
238
239    // wrt-rd     EVT15             = 0xFFE0203C
240LD32(p0, 0xFFE0203C);
241LD32(r0, 0xFFFFABC6);
242    [ P0 ] = R0;
243
244    // wrt-rd  EVT_OVERRIDE:9 bits  = 0xFFE02100
245LD32(p0, 0xFFE02100);
246LD32(r0, 0x000001ff);
247    [ P0 ] = R0;
248
249    // wrt-rd  IMASK: 16 bits       = 0xFFE02104
250LD32(p0, 0xFFE02104);
251LD32(r0, 0x00000fe0);
252    [ P0 ] = R0;
253
254
255    // wrt-rd  IPEND: 16 bits, rw=0 = 0xFFE02108
256LD32(p0, 0xFFE02108);
257LD32(r0, 0x00000000);
258  //[p0] = r0;
259RAISE 12;
260RAISE 13;
261
262    // wrt-rd  ILAT: 16 bits, rw=0  = 0xFFE0210C
263LD32(p0, 0xFFE0210C);
264LD32(r0, 0x00000000);
265  //[p0] = r0;
266CSYNC;
267//*** read ops
268P1.L = DATA0;
269P1.H = DATA0;
270
271LD32(p0, 0xFFE02000);
272    P2 = 16;
273LSETUP ( start1 , end1 ) LC0 = P2;
274start1:
275      R0 = [ P0 ++ ];
276end1: [ P1 ++ ] = R0;
277//nop;
278P1.L = DATA0;
279P1.H = DATA0;
280    R0 = [ P1 ++ ];
281    R1 = [ P1 ++ ];
282    R2 = [ P1 ++ ];
283    R3 = [ P1 ++ ];
284    R4 = [ P1 ++ ];
285    R5 = [ P1 ++ ];
286    R6 = [ P1 ++ ];
287    R7 = [ P1 ++ ];
288CHECKREG(r0, 0x00000000);
289CHECKREG(r1, 0x00000000);
290CHECKREG(r2, 0xE1DE5D1C);
291CHECKREG(r3, 0x9CC20332);
292CHECKREG(r4, 0x00000000);
293CHECKREG(r5, 0x55552345);
294CHECKREG(r6, 0x66663456);
295CHECKREG(r7, 0x77774567);
296    R0 = [ P1 ++ ];
297    R1 = [ P1 ++ ];
298    R2 = [ P1 ++ ];
299    R3 = [ P1 ++ ];
300    R4 = [ P1 ++ ];
301    R5 = [ P1 ++ ];
302    R6 = [ P1 ++ ];
303    R7 = [ P1 ++ ];
304CHECKREG(r0, 0x88885678);
305CHECKREG(r1, 0x99996789);
306CHECKREG(r2, 0xAAAA1234);
307CHECKREG(r3, 0xBBBBABC6);
308CHECKREG(r4, 0xCCCCABC6);
309CHECKREG(r5, 0xDDDDABC6);
310CHECKREG(r6, 0xEEEEABC6);
311CHECKREG(r7, 0xFFFFABC6);
312
313dbg_pass;            // End the test
314
315//*********************************************************************
316
317//
318// Handlers for Events
319//
320
321EHANDLE:            // Emulation Handler 0
322RTE;
323
324RHANDLE:            // Reset Handler 1
325RTI;
326
327NHANDLE:            // NMI Handler 2
328    R0 = 2;
329RTN;
330
331XHANDLE:            // Exception Handler 3
332    R7 = 0x00006789 (X);
333RTX;
334
335HWHANDLE:           // HW Error Handler 5
336    R2 = 5;
337RTI;
338
339THANDLE:            // Timer Handler 6
340    R3 = 6;
341RTI;
342
343I7HANDLE:           // IVG 7 Handler
344    R4 = 7;
345RTI;
346
347I8HANDLE:           // IVG 8 Handler
348    R5 = 8;
349RTI;
350
351I9HANDLE:           // IVG 9 Handler
352    R6 = 9;
353RTI;
354
355I10HANDLE:          // IVG 10 Handler
356    R7 = 10;
357RTI;
358
359I11HANDLE:          // IVG 11 Handler
360    R0 = 11;
361RTI;
362
363I12HANDLE:          // IVG 12 Handler
364    R1 = 12;
365RTI;
366
367I13HANDLE:          // IVG 13 Handler
368    R2 = 13;
369RTI;
370
371I14HANDLE:          // IVG 14 Handler
372    R3 = 14;
373RTI;
374
375I15HANDLE:          // IVG 15 Handler
376    R4 = 15;
377RTI;
378
379NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
380
381//
382// Data Segment
383//
384
385.section MEM_DATA_ADDR_1,"aw"
386DATA0:
387.dd 0x000a0000
388.dd 0x000b0001
389.dd 0x000c0002
390.dd 0x000d0003
391.dd 0x000e0004
392.dd 0x000f0005
393.dd 0x00100006
394.dd 0x00200007
395.dd 0x00300008
396.dd 0x00400009
397.dd 0x0050000a
398.dd 0x0060000b
399.dd 0x0070000c
400.dd 0x0080000d
401.dd 0x0090000e
402.dd 0x0100000f
403.dd 0x02000010
404.dd 0x03000011
405.dd 0x04000012
406.dd 0x05000013
407.dd 0x06000014
408.dd 0x001a0000
409.dd 0x001b0001
410.dd 0x001c0002
411// Stack Segments (Both Kernel and User)
412
413    .space (STACKSIZE);
414KSTACK:
415
416    .space (STACKSIZE);
417USTACK:
418