1//Original:/proj/frio/dv/testcases/core/c_interr_timer/c_interr_timer.dsp
2// Spec Reference: interrupt on HW TIMER
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10//
11// Include Files
12//
13
14include(std.inc)
15include(selfcheck.inc)
16
17// Defines
18
19#ifndef TCNTL
20#define TCNTL            0xFFE03000
21#endif
22#ifndef TPERIOD
23#define TPERIOD          0xFFE03004
24#endif
25#ifndef TSCALE
26#define TSCALE           0xFFE03008
27#endif
28#ifndef TCOUNT
29#define TCOUNT           0xFFE0300c
30#endif
31#ifndef EVT
32#define EVT              0xFFE02000
33#endif
34#ifndef EVT15
35#define EVT15            0xFFE0203c
36#endif
37#ifndef EVT_OVERRIDE
38#define EVT_OVERRIDE     0xFFE02100
39#endif
40#ifndef ITABLE
41#define ITABLE           0x000FF000
42#endif
43#ifndef PROGRAM_STACK
44#define PROGRAM_STACK    0x000FF100
45#endif
46#ifndef STACKSIZE
47#define STACKSIZE        0x00000300
48#endif
49
50// Boot code
51
52 BOOT :
53INIT_R_REGS(0);                             // Initialize Dregs
54INIT_P_REGS(0);                             // Initialize Pregs
55
56     // CHECK_INIT(p5,   0xE0000000);
57include(symtable.inc)
58CHECK_INIT_DEF(p5);
59
60
61LD32(sp, 0x000FF200);
62LD32(p0, EVT);              // Setup Event Vectors and Handlers
63
64LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
65        [ P0 ++ ] = R0;
66
67LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
68        [ P0 ++ ] = R0;
69
70LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
71        [ P0 ++ ] = R0;
72
73LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
74        [ P0 ++ ] = R0;
75
76        [ P0 ++ ] = R0;                // IVT4 not used
77
78LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
79        [ P0 ++ ] = R0;
80
81LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
82        [ P0 ++ ] = R0;
83
84LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
85        [ P0 ++ ] = R0;
86
87LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
88        [ P0 ++ ] = R0;
89
90LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
91        [ P0 ++ ] = R0;
92
93LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
94        [ P0 ++ ] = R0;
95
96LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
97        [ P0 ++ ] = R0;
98
99LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
100        [ P0 ++ ] = R0;
101
102LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
103        [ P0 ++ ] = R0;
104
105LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
106        [ P0 ++ ] = R0;
107
108LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
109        [ P0 ++ ] = R0;
110
111LD32(p0, EVT_OVERRIDE);
112        R0 = 0;
113        [ P0 ++ ] = R0;
114        R0 = -1;     // Change this to mask interrupts (*)
115        [ P0 ] = R0;   // IMASK
116
117LD32_LABEL(p1, START);
118
119LD32(p0, EVT15);
120        [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
121CSYNC;
122RAISE 15;    // after we RTI, INT 15 should be taken
123
124LD32_LABEL(r7, START);
125RETI = r7;
126NOP;        // Workaround for Bug 217
127RTI;
128NOP;
129NOP;
130NOP;
131NOP;
132NOP;
133NOP;
134NOP;
135NOP;
136DUMMY:
137	  NOP;
138NOP;
139NOP;
140NOP;
141NOP;
142NOP;
143NOP;
144NOP;
145NOP;
146NOP;
147
148//.code 0x200
149 START :
150        R7 = 0x0;
151        R6 = 0x1;
152        [ -- SP ] = RETI;        // Enable Nested Interrupts
153
154WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON TMPWR(0) (active state)
155WR_MMR(TPERIOD, 0x00000050, p0, r0);
156    //  WR_MMR(TCOUNT,  0x00000013, p0, r0);
157WR_MMR(TCOUNT,  0x00000000, p0, r0);
158WR_MMR(TSCALE,  0x00000000, p0, r0);
159CSYNC;
160        // Read the contents of the Timer
161
162RD_MMR(TPERIOD, p0, r2);
163CHECKREG(r2,    0x00000050);
164
165
166WR_MMR(TCNTL,   0x00000003, p0, r0);    // enable Timer (TMPWR(0), TMREN(1))
167CSYNC;                                  // TIMER interrupt
168
169RD_MMR(TCOUNT, p0, r3);
170CSYNC;
171CHECKREG(r3,    0x00000000);
172CHECKREG(r7,    0x00000001);
173WR_MMR(TCNTL,   0x00000001, p0, r0);    // enable Timer (TMPWR(0), TMREN(1)=0)
174WR_MMR(TCOUNT,  0x00000013, p0, r0);
175WR_MMR(TCNTL,   0x00000003, p0, r0);    // enable Timer (TMPWR(0), TMREN(1))
176CSYNC;
177NOP; NOP; NOP;
178NOP; NOP; NOP;
179NOP; NOP; NOP;
180NOP; NOP; NOP;
181NOP; NOP; NOP;
182NOP; NOP; NOP;
183NOP; NOP; NOP;
184NOP; NOP; NOP;
185RD_MMR(TCOUNT, p0, r4);
186CHECKREG(r4,    0x00000000);
187
188RD_MMR(TCNTL, p0, r5);
189CHECKREG(r5,    0x0000000B);
190
191WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
192CSYNC;
193NOP;
194WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON Timer Power
195WR_MMR(TCNTL,   0x00000003, p0, r0);        // Turn ON Power, EN -> interr
196CSYNC;
197CHECKREG(r7,    0x00000003);              // 3 interr already happened
198        R7 = 0;                                     // reset r7
199WR_MMR(TPERIOD, 0x00000040, p0, r0);
200WR_MMR(TCOUNT,  0x00000013, p0, r0);
201WR_MMR(TSCALE,  0x00000002, p0, r0);
202WR_MMR(TCNTL,   0x00000007, p0, r0);        // Turn ON Timer auto load
203CSYNC;
204NOP;
205NOP;
206NOP;
207NOP;
208NOP;
209NOP;
210NOP;
211NOP;
212NOP;
213NOP;
214NOP;
215NOP;
216NOP;
217NOP;
218NOP;
219JUMP.S label4;
220        R4.L = 0x1111;                             // Will be killed
221        R4.H = 0x1111;                             // Will be killed
222NOP;
223NOP;
224NOP;
225label5: R5.H = 0x7777;
226        R5.L = 0x7888;
227JUMP.S label6;
228        R5.L = 0x1111;                             // Will be killed
229        R5.H = 0x1111;                             // Will be killed
230NOP;
231NOP;
232NOP;
233NOP;
234NOP;
235NOP;
236label4: R4.H = 0x5555;
237        R4.L = 0x6666;
238NOP;
239JUMP.S label5;
240        R5.L = 0x2222;     // Will be killed
241        R5.H = 0x2222;     // Will be killed
242NOP;
243NOP;
244NOP;
245NOP;
246label6: R3.H = 0x7999;
247        R3.L = 0x7aaa;
248NOP;
249NOP;
250NOP;
251NOP;
252NOP;
253NOP;
254NOP;
255                                                    // With auto reload
256        // Read the contents of the Timer
257
258RD_MMR(TPERIOD, p0, r2);
259CHECKREG(r2,    0x00000040);
260
261//      CHECKREG(r7,    0x00000002);
262CC = R7 == 0;
263IF !CC JUMP LABEL1;
264WR_MMR(TPERIOD, 0x00000030, p0, r0);   // SHOULD NOT EXECUTE
265
266LABEL1:
267
268NOP; NOP; NOP; NOP; NOP;
269NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
270NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
271NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
272NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
273NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
274
275
276RD_MMR(TCNTL , p0, r3);
277CHECKREG(r3,    0x0000000F);
278
279
280WR_MMR(TCNTL,   0x00000003, p0, r0);        // Turn ON Timer
281CSYNC;
282RD_MMR(TPERIOD, p0, r2);
283CHECKREG(r2,    0x00000040);
284
285
286NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
287NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
288NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
289NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
290NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
291NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
292NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
293NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
294NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
295NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
296NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
297NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
298NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
299NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
300NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
301NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
302NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
303RD_MMR(TCOUNT, p0, r4);
304CHECKREG(r4,    0x00000000);
305
306RD_MMR(TCNTL, p0, r5);
307CHECKREG(r5,    0x0000000B);
308
309WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
310CSYNC;
311NOP; NOP; NOP;
312
313WR_MMR(TPERIOD, 0x00000060, p0, r0);
314CSYNC;
315NOP;
316RD_MMR(TPERIOD, p0, r6);
317CHECKREG(r6,    0x00000060);
318
319
320
321
322dbg_pass;        // Call Endtest Macro
323
324
325
326//*********************************************************************
327//
328// Handlers for Events
329//
330
331EHANDLE:            // Emulation Handler 0
332RTE;
333
334RHANDLE:            // Reset Handler 1
335RTI;
336
337NHANDLE:            // NMI Handler 2
338RTN;
339
340XHANDLE:            // Exception Handler 3
341RTX;
342
343HWHANDLE:           // HW Error Handler 5
344RTI;
345
346THANDLE:            // Timer Handler 6
347        R7 = R7 + R6;
348RTI;
349
350I7HANDLE:           // IVG 7 Handler
351RTI;
352
353I8HANDLE:           // IVG 8 Handler
354RTI;
355
356I9HANDLE:           // IVG 9 Handler
357RTI;
358
359I10HANDLE:          // IVG 10 Handler
360RTI;
361
362I11HANDLE:          // IVG 11 Handler
363RTI;
364
365I12HANDLE:          // IVG 12 Handler
366RTI;
367
368I13HANDLE:          // IVG 13 Handler
369RTI;
370
371I14HANDLE:          // IVG 14 Handler
372RTI;
373
374I15HANDLE:          // IVG 15 Handler
375        R5 = RETI;
376        P0 = R5;
377JUMP ( P0 );
378RTI;
379
380.section MEM_DATA_ADDR_1,"aw"
381
382.space (STACKSIZE);
383STACK:
384NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
385