1//Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp
2# mach: bfin
3
4.include "testutils.inc"
5	start
6
7
8// Spec Reference: dsp32shiftimm ashift: mix
9
10
11
12imm32 r4, 0x00000000;
13imm32 r5, 0x00000000;
14imm32 r6, 0x00000000;
15imm32 r7, 0x00000000;
16
17// Ashift : positive data, count (+)=left (half reg)
18imm32 r0, 0x00010001;
19imm32 r1, 1;
20imm32 r2, 0x00020002;
21imm32 r3, 2;
22R4.H = R0.H << 1;
23R4.L = R0.L << 1; /* r4 = 0x00020002 */
24R5.H = R2.H << 2;
25R5.L = R2.L << 2; /* r5 = 0x00080008 */
26R6 = R0 << 1 (V); /* r6 = 0x00020002 */
27R7 = R2 << 2 (V); /* r7 = 0x00080008 */
28CHECKREG r4, 0x00020002;
29CHECKREG r5, 0x00080008;
30CHECKREG r6, 0x00020002;
31CHECKREG r7, 0x00080008;
32
33imm32 r1, 3;
34imm32 r3, 4;
35R6 = R0 << 3; /* r6 = 0x00080010 */
36R7 = R2 << 4;
37CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */
38CHECKREG r7, 0x00200020;
39
40A0 = 0;
41A0.L = R0.L;
42A0.H = R0.H;
43A0 = A0 << 3; /* a0 = 0x00080008 */
44R5 = A0.w; /* r5 = 0x00080008 */
45CHECKREG r5, 0x00080008;
46
47imm32 r4, 0x30000003;
48imm32 r1, 1;
49R5 = R4 << 1; /* r5 = 0x60000006 */
50
51imm32 r1, 2;
52R6 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */
53CHECKREG r5, 0x60000006;
54CHECKREG r6, 0xc000000c;
55
56
57// Ashift : count (-)=right (half reg)
58imm32 r0, 0x10001000;
59imm32 r1, -1;
60imm32 r2, 0x10001000;
61imm32 r3, -2;
62R4.H = R0.H >>> 1;
63R4.L = R0.L >>> 1; /* r4 = 0x08000800 */
64R5.H = R2.H >>> 2;
65R5.L = R2.L >>> 2; /* r4 = 0x04000400 */
66R6 = R0 >>> 1 (V); /* r4 = 0x08000800 */
67R7 = R2 >>> 2 (V); /* r4 = 0x04000400 */
68CHECKREG r4, 0x08000800;
69CHECKREG r5, 0x04000400;
70CHECKREG r6, 0x08000800;
71CHECKREG r7, 0x04000400;
72
73// Ashift : (full reg)
74imm32 r1, -3;
75imm32 r3, -4;
76R6 = R0 >>> 3; /* r6 = 0x02000200 */
77R7 = R2 >>> 4; /* r7 = 0x01000100 */
78CHECKREG r6, 0x02000200;
79CHECKREG r7, 0x01000100;
80
81// NEGATIVE
82// Ashift : NEGATIVE data, count (+)=left (half reg)
83imm32 r0, 0xc00f800f;
84imm32 r1, 1;
85imm32 r2, 0xe00fe00f;
86imm32 r3, 2;
87R4.H = R0.H << 1;
88R4.L = R0.L << 1 (S); /* r4 = 0x801e801e */
89R5.H = R2.H << 2;
90R5.L = R2.L << 2; /* r4 = 0x803c803c */
91CHECKREG r4, 0x801e8000;
92CHECKREG r5, 0x803c803c;
93
94imm32 r0, 0xc80fe00f;
95imm32 r2, 0xe40fe00f;
96imm32 r1, 4;
97imm32 r3, 5;
98R6 = R0 << 4; /* r6 = 0x80fe00f0 */
99R7 = R2 << 5; /* r7 = 0x81fc01e0 */
100CHECKREG r6, 0x80fe00f0;
101CHECKREG r7, 0x81fc01e0;
102
103imm32 r0, 0xf80fe00f;
104imm32 r2, 0xfc0fe00f;
105R6 = R0 << 4 (S); /* r6 = 0x80fe00f0 */
106R7 = R2 << 5 (S); /* r7 = 0x81fc01e0 */
107CHECKREG r6, 0x80fe00f0;
108CHECKREG r7, 0x81fc01e0;
109
110imm32 r0, 0xc80fe00f;
111imm32 r2, 0xe40fe00f;
112R6 = R0 << 4 (S); /* r6 = 0x80000000 zero bubble tru MSB */
113R7 = R2 << 5 (S); /* r7 = 0x80000000 */
114CHECKREG r6, 0x80000000;
115CHECKREG r7, 0x80000000;
116
117imm32 r0, 0xFFFFFFF4;
118imm32 r2, 0xFFF00001;
119R6 = R0 << 31 (S); /* r6 = 0x80000000 */
120R7 = R2 << 31 (S); /* r7 = 0x80000000 */
121CHECKREG r6, 0x80000000;
122CHECKREG r7, 0x80000000;
123
124
125// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok
126imm32 r0, 0x80f080f0;
127imm32 r1, -1;
128imm32 r2, 0x80f080f0;
129imm32 r3, -2;
130R4.H = R0.H >>> 1;
131R4.L = R0.L >>> 1; /* r4 = 0xc078c078 */
132R5.H = R2.H >>> 2;
133R5.L = R2.L >>> 2; /* r4 = 0xe03ce03c */
134CHECKREG r4, 0xc078c078;
135CHECKREG r5, 0xe03ce03c;
136R6 = R0 >>> 1 (V); /* r6 = 0xc078c078 */
137R7 = R2 >>> 2 (V); /* r7 = 0xe03ce03c */
138CHECKREG r6, 0xc078c078;
139CHECKREG r7, 0xe03ce03c;
140
141imm32 r1, -3;
142imm32 r3, -4;
143R6 = R0 >>> 3; /* r6 = 0xf01e101e */
144R7 = R2 >>> 4; /* r7 = 0xf80f080f */
145CHECKREG r6, 0xf01e101e;
146CHECKREG r7, 0xf80f080f;
147
148
149pass
150