1//Original:/testcases/core/c_dsp32shift_amix/c_dsp32shift_amix.dsp
2// Spec Reference: dsp32shift ashift mix
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8// Ashift (Arithmetic ) retain the sign bit (0-->0, 1-->1)
9
10imm32 r4, 0x00000000;
11imm32 r5, 0x00000000;
12imm32 r6, 0x00000000;
13imm32 r7, 0x00000000;
14
15// Ashift : positive data, count (+)=left (half reg)
16imm32 r0, 0x00010001;
17imm32 r1, 1;
18imm32 r2, 0x00020002;
19imm32 r3, 2;
20R4.H = ASHIFT R0.H BY R1.L;
21R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
22R5.H = ASHIFT R2.H BY R3.L;
23R5.L = ASHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
24R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
25R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
26CHECKREG r4, 0x00020002;
27CHECKREG r5, 0x00080008;
28CHECKREG r6, 0x00020002;
29CHECKREG r7, 0x00080008;
30
31// Ashift : (full reg)
32imm32 r1, 3;
33imm32 r3, 4;
34R6 = ASHIFT R0 BY R1.L; /* r6 = 0x00080010 */
35R7 = ASHIFT R2 BY R3.L;
36CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */
37CHECKREG r7, 0x00200020;
38
39A0 = 0;
40A0.L = R0.L;
41A0.H = R0.H;
42A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00080008 */
43R5 = A0.w; /* r5 = 0x00080008 */
44
45CHECKREG r5, 0x00080008;
46imm32 r4, 0x30000003;
47imm32 r1, 1;
48R5 = ASHIFT R4 BY R1.L; /* r5 = 0x60000006 */
49CHECKREG r5, 0x60000006;
50imm32 r1, 2;
51R5 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */
52CHECKREG r5, 0xc000000c;
53
54
55// Ashift : count (-)=right (half reg)
56imm32 r0, 0x10001000;
57imm32 r1, -1;
58imm32 r2, 0x10001000;
59imm32 r3, -2;
60R4.H = ASHIFT R0.H BY R1.L;
61R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x08000800 */
62R5.H = ASHIFT R2.H BY R3.L;
63R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0x04000400 */
64R6 = ASHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */
65R7 = ASHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */
66CHECKREG r4, 0x08000800;
67CHECKREG r5, 0x04000400;
68CHECKREG r6, 0x08000800;
69CHECKREG r7, 0x04000400;
70
71// Ashift : (full reg)
72imm32 r1, -3;
73imm32 r3, -4;
74R6 = ASHIFT R0 BY R1.L; /* r6 = 0x02000200 */
75R7 = ASHIFT R2 BY R3.L; /* r7 = 0x01000100 */
76CHECKREG r6, 0x02000200;
77CHECKREG r7, 0x01000100;
78
79// NEGATIVE
80// Ashift : NEGATIVE data, count (+)=left (half reg)
81imm32 r0, 0xc00f800f;
82imm32 r1, 1;
83imm32 r2, 0xe00fe00f;
84imm32 r3, 2;
85R4.H = ASHIFT R0.H BY R1.L;
86R4.L = ASHIFT R0.L BY R1.L (S); /* r4 = 0x801e801e */
87R5.H = ASHIFT R2.H BY R3.L;
88R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0x803c803c */
89CHECKREG r4, 0x801e8000;
90CHECKREG r5, 0x803c803c;
91
92imm32 r0, 0xc80fe00f;
93imm32 r2, 0xe40fe00f;
94imm32 r1, 4;
95imm32 r3, 5;
96R6 = ASHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
97R7 = ASHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
98CHECKREG r6, 0x80fe00f0;
99CHECKREG r7, 0x81fc01e0;
100
101imm32 r0, 0xf80fe00f;
102imm32 r2, 0xfc0fe00f;
103R6 = ASHIFT R0 BY R1.L (S); /* r6 = 0x80fe00f0 */
104R7 = ASHIFT R2 BY R3.L (S); /* r7 = 0x81fc01e0 */
105CHECKREG r6, 0x80fe00f0;
106CHECKREG r7, 0x81fc01e0;
107
108imm32 r0, 0xc80fe00f;
109imm32 r2, 0xe40fe00f;
110R6 = ASHIFT R0 BY R1.L (S); /* r6 = 0x80000000 zero bubble tru MSB */
111R7 = ASHIFT R2 BY R3.L (S); /* r7 = 0x80000000 */
112CHECKREG r6, 0x80000000;
113CHECKREG r7, 0x80000000;
114
115
116// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok
117imm32 r0, 0x80f080f0;
118imm32 r1, -1;
119imm32 r2, 0x80f080f0;
120imm32 r3, -2;
121R4.H = ASHIFT R0.H BY R1.L;
122R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0xc078c078 */
123R5.H = ASHIFT R2.H BY R3.L;
124R5.L = ASHIFT R2.L BY R3.L; /* r4 = 0xe03ce03c */
125CHECKREG r4, 0xc078c078;
126CHECKREG r5, 0xe03ce03c;
127R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0xc078c078 */
128R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0xe03ce03c */
129CHECKREG r6, 0xc078c078;
130CHECKREG r7, 0xe03ce03c;
131
132// Ashift : (full reg)
133imm32 r1, -3;
134imm32 r3, -4;
135R6 = ASHIFT R0 BY R1.L; /* r6 = 0xf01e101e */
136R7 = ASHIFT R2 BY R3.L; /* r7 = 0xf80f080f */
137CHECKREG r6, 0xf01e101e;
138CHECKREG r7, 0xf80f080f;
139
140
141
142pass
143